Digital Systems

1
14
Digital Systems
2
Figure 14.1 RS flip-flop symbol and truth table
3
Figure 14.2 Timing diagram for the RS flip-flop
4
Figure 14.3 Logic gate implementation of the RS
flip-flop
5
Figure 14.4 RS flip-flop with enable, present,
and clear lines
6
Figure 14.5 Data latch and associated timing
diagram
7
Figure 14.6 D flip-flop functional diagram,
symbol, and timing waveforms
8
Figure 14.7 JK flip-flop functional diagram and
device symbol
9
Figure 14.8 Truth table for JK flip-flop
10
Figure 14.10 Binary up counter functional
representation, state table, and timing waveforms
11
Figure 14.11 Decade counter
12
Figure 14.12 Ripple counter
1
1
1
13
Figure 14.15 Three-bit synchronous counter
14
Figure 14.16 Ring counter
input
15
Figure 14.21 Four-bit parallel register
16
Figure 14.22 Four-bit shift register
17
Figure 14.24
18
Figure 14.26 Three-bit binary counter and state
diagram
19
Figure 14.27 State diagram of a modulo-4 up-down
counter
20
Figure 14.28 Karnaugh maps for flip-flop inputs
in modulo-4 counter
21
Figure 14.29 Implementation of modulo-4 counter
22
Figure 14.30 Structure of a digital data
acquisition and control system