Test and Verification of Digital Systems

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Test and Verification of Digital Systems

• Jaan Raik

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Test and Verification of Digital Systems

• Digital systems design and test group
• Motivation Why test and verification?
• Decision Diagram (DD) modeling
• High-level decision diagrams
• Structural BDDs
• DD-based test and verification methods
• High-level test pattern generation
• Assertion-based verification

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Digital systems design and test group

• Head of the group Prof. Raimund Ubar
• Prof. Peeter Ellervee, Synthesis
• Dr. Gert Jervan, Built-in self-test
• Dr. Artur Jutman, Circuit board systems test
• 15 PhD students

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Moores Law (1965)
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Moores Law (1965)
Year of Introduction Transistors 4004
1971 2,250 8008 1972 2,500 8080
1974 5,000 8086 1978 29,000 286
1982 120,000 Intel386 processor 1985
275,000 Intel486 processor 1989
1,180,000 Intel Pentium processor 1993
3,100,000 Intel Pentium II processor 1997
7,500,000 Intel Pentium III processor 1999
24,000,000 Intel Pentium 4 processor 2000
42,000,000 Intel Itanium processor 2002
220,000,000 Intel Itanium 2 processor 2003
410,000,000
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Automation ...

• and formal methods
• Productivity gap
• Technology 58 /year
• Design 21 /year

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Why test and verification?

• Design productivity gap. Technology develops
  faster than design tools.
• Test and verification takes an ever-increasing
  portion (70 ... 85 ) of total design expenses
• New paradigms (SoC/NoC, ESL,...) needed to bring
  down the costs
• Need for more efficient test and verification
  methods

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Alternative decision diagram models

• High-level decision diagrams (HLDD)
• Structural binary decision diagrams (SBDD)

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HLDDs background

• At logic-level, BDDs have been used since
  mid-1980s (Bryant 86)
• At RT-level, assignment decision diagrams
  proposed (Gajski 92)
• Raimund Ubar proposed HLDD models at the end of
  1970s
• Since then TUT has carried out research on
  applying HLDDs and BDDs in test

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HLDDs data structure

• HLDDs are graph representations of discrete
  functions
• Directed, acyclic graph with a single root node
• Nodes labeled by variables integer, Boolean,
  enumeration, function types
• Simulation by traversing the DD starting from the
  root node

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HLDDs an abstract example
HLDD for a function yf(x1,x2,x3,x4)

x15 x22 ? yx15
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HLDDs digital systems
Decision diagrams for the datapath

a) Datapath architecture
b) Decision diagram
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HLDDs digital systems
Decision diagrams for finite state automata

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HLDDs advantages

• Generalization of BDD (unlike ADD!)
• Functional graph representation
• Simulation by traversal
• Cause-effect relationships easy to detect
• Scalable
• Worst case complexity (time, space) is linear to
  square, depending on level

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HLDD based ATPG DECIDER

• The prototype of DECIDER was first presented at
  DATE 1999.
• The novelty utilization of circuit model of
  HLDDs
• Combines hierarchical and functional fault models
• Dedicated fault models for functional units,
  multiplexers and comparison operators

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DECIDER

• Top-down approach

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DECIDER symbolic constraints

• High-level test generation constraints
• Path activation
• Propagation
• Justification

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DECIDER experimental results
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History of BDDs

• 1959 Lee, binary branching programs
• 1976 Ubar, alternative graphs alias structural
  BDDs
• 1978 Akers, proposes BDD
• 1985 Bryant, ROBDD
• ROBDD starts the BDD boom

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Logic circuit and its SBDD
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Fault simulation. Stuck-at fault model

• Stuck-at fault model
• Only one circuit line is faulty.
• The faulty line is permanently stuck to 0 or 1.
• Stuck-at fault simulation for a circuit line l is
  equivalent
• to calculating the Boolean derivative for
  variable xl.

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Fault simulation. SBDD model
We say that fault stuck-at ai in node vj , where
label(vj) is xi, is covered by a vector a1, ,
ai, , an iff all of the three conditions are
satised 1. There exists an activated path from
the root node to vj . 2. There exists an
activated path from high(vj) to sink 1. 3. There
exists an activated path from low(vj) to sink 0.
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Fault simulation. SBDD model
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Structural BDDs. Latest results

• Research on SBDD model. Co-operation with Univ.
  Tartu (Prof. M. Tombak, A. Peder).
• Ultra-fast fault simulator combining Boolean
  derivatives and SBDD simulation
• Assertion checker
• Code coverage analysis

HLDD based verification. Latest results