MuP21 Microprocessor

1
MuP21 Microprocessor

• Introduction to MISC

2
Post-RISC Era

• There is no longer a clear distinction between
  RISC and CISC microprocessors.
• CISC (Complicated Instruction Computing), like
  the x86 family, persists due to upward
  compatibility.
• RISC (Reduced Instruction Computing) has become
  much more complicated.
• David Ditzel
• "The MIPS R10,000 and HP PA-8000 seem much more
  complex to me than today's standard CISC
  architecture, which is the Pentium II. So where
  is the advantage of RISC, if the chips aren't as
  simple anymore?"

3
Introducing MISC

• Principles borrowed from RISC
• Simple instruction set is faster
• Complicated memory accessing instructions are not
  necessary
• Simpler processor is easier to design and to
  build
• A desire to push the principle of simplicity to
  its limits.

4
MISC

• Minimum Instruction Set Computing
• What is the minimum set of instructions in a
  practical microprocessor?
• Somewhere between 16 and 32
• A convenient choice is 32 which leads a
  microprocessor to 5 bit instructions.

5
MUP21 Chip

• Highly integrated multiprocessor chip
• Main CPU with video and memory coprocessor
• Targeted for applications in video displays, CAD
  design, communication, video games, and embedded
  systems.

6
MuP21 Instruction Set

• Only 24 5-bit instructions
• Transfer Instructions
• JUMP, CALL, RET, JZ, JCZ
• Memory Instructions
• LOAD, STORE, LOADP, STOREP, LIT
• ALU Instructions
• COM, XOR, AND, ADD, SHL, SHR, ADDNZ
• Register Instructions
• LOADA, STOREA, DUP, DROP, OVER, NOP

7
Missing Instructions

• There is an ADD, but no SUB
• Subtraction can be accomplished by taking the
  compliment (COM) and then doing addition.
• There is XOR, but no OR
• OR can be accomplished by compliment (COM),
  addition, and then XOR.
• Like RISC, MISC avoids unnecessary instructions
  that can be synthesized from simpler
  instructions.

8
Instruction Format

• 5-bits instructions corresponding to the 24
  different instructions.
• 4 instructions per each 20-bit word fed from
  memory. (natural instruction pipeline)
• After 4 instructions are executed, the slower
  external memory is ready to supply the next set
  of 4 instructions.
• The processor can be four times faster than the
  memory. Fast cache memory and the associated
  control circuitry are not needed.

9
Execution

• Unlike RISC, which requires a 4 step execution
  due to the need to decode the instruction and
  select operand registers.
• MISC needs only two step execution
• Read a 20-bit word from memory and latch it into
  the instruction latch.
• Execute the 5-bit instructions by latching proper
  results into the T register.

10
MuP21 Architecture

• First of a series of MISC microprocessor
• Housed in a 40 pin DIP
• Silicon die is less than 100 mils square
• Result
• Constrained to a 20 bit microprocessor
• Not enough I/O pins to support a processor with
  wider data and address buses.

11
MuP21 Architecture (Cont.)

• Dual Stack based processor
• Data Stack and Return Stack
• More advantageous than a register based processor
  because the source and destination registers are
  defined in hardware and no register decoding is
  necessary.
• However, stack compilers are not that efficient.
• 21-bit CPU Core
• Video Coprocessor
• Memory Coprocessor

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Primary Memory - DRAM

• Advantage
• DRAM offers the best bit density and lowest cost
  per bit
• Disadvantage
• Needs to boot from ROM or 8 bit memory devices
• Needs to address various I/O devices
• Result
• A memory coprocessor is required in order to
  handle the buses and to generate proper signals
  to memory and I/O devices

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CPU Components

• A Return Stack to nest subroutine return
  addresses
• A Data Stack to store parameters passing between
  subroutines
• A T (Top) Register as the central holding
  register for operands
• An ALU which takes operands from T and the top of
  Data Stack and returns the results of ALU
  operation to T Register
• An A (Address) Register to hold a memory address
  for fetching or storing data from/to memory
• A PC (Program Counter) Register to hold the
  address of the next instruction
• An Instruction Latch which holds four 5-bit
  instructions to be executed in sequence

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ALU Execution

• The ALU instructions can be executed very fast
  because operands are taken from the T register
  and the top of the data stack, and the results
  are returned to the T register.
• Once the data in the T register on the top of the
  data stack are stable, ALU results from COM (of
  T), SHL, SHR, XOR, AND, ADD, and conditional ADD
  are generated spontaneously.
• The ALU instruction only selects the proper
  results and gates them back into the T register.

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Video Coprocessor

• Runs in parallel with main processor to display
  video frames stored in the primary DRAM memory.
• Reads 20 bits word from DRAM and interprets them
  as four 5 bits instructions.
• Can generate NTSC or PAL signal to drive a color
  TV monitor.

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Video Coprocessor - Instruction Set

• 5-bit instruction format 0 I G R B
• I,G,R,B stands for intensity, green, red, and
  blue respectively
• Instruction set for video processor
• Opcode Hex Name Slot Cycles
• B 00 Black x 1
• S 17 Sync x 1
• R 1F Refresh 2 1
• K 13 Skip 0 1
• C 15 Burst x 1
• P 0x Pixel x 1
• J 18 Jump 0 0

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Memory Coprocessor

• Mostly hidden from the user
• Arbitrates DRAM access requests
• The memory request from the video coprocessor has
  priority over that from the main CPU.
• Generates the proper control signals to DRAM and
  SRAM memories as well as I/O devices.
• Controls the address and data buses to the memory
  and I/O devices.
• When accessing DRAM memory, the 20-bit addresses
  are multiplexed over pins A0-A9, and data bus
  consists of D0-D9 and AD10-AD19.
• When accessing SRAM memory during booting, the
  address bus consists of A0-A9 and AD10-AD19,
  while the 8-bit data bus is on D0-D7.
• When accessing I/O devices, the addresses are on
  A0-A9, and data are on D0-D9 and AD10-AD19.

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Memory and I/O Access

• Controlled by address lines and 2 bits in
  Configuration Register.
• MuP21 maintains a 21 bits data/address bus.
• Bit 20 is the carry bit in ALU operations.
• Selects DRAM when low, and SRAM or I/O when high.

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Memory Map

• Memory map of memory and I/O devices
• Address Device
• 0-FFFFF 20-bit DRAM memory
• 12000-1203FF Slow 20-bit I/O
  devices
• 14000 Configuration
  Register
• 16000-1603FF Fast 20-bit I/O
  devices
• 18000-1BFFFF Fast 8-bit SRAM
  memory
• 1C000-1FFFFF Slow 8-bit SRAM
  memory
• According to the memory map, MuP21 addresses
  directly only 256 KB of SRAM memory.
• However, Bits 18-19 in the Configuration Register
  are forced on the address bus when reading or
  writing SRAM.
• This paging mechanism allows MuP21 to access 1 MB
  of external SRAM memory.

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Performance

• Executes instructions at a speed of 10ns per
  instruction.
• Peak execution rate is thus 100 MIPS.
• Accessing DRAM slows it to 80 MIPS.
• The limited 24 instructions is adequate in
  implementing certain applications
• Quite elaborate operating systems
• And demonstration programs

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MISC Chips - Applications

• Variety of potential application due to key
  design features like
• High speed, low power consumption, and large
  addressing space
• Potential applications
• Advanced video games
• TV signage
• Video test pattern generators
• CAD design system
• Telephone switching system
• Handheld computers
• High speed communications systems
• Intelligent hard disk controllersRobotic
  controllers

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Improvement Possibilities

• MuP21 runs at peak speed of 100 MIPS with 1.2
  micron CMOS process.
• Double speed with 0.8 micron or even triple with
  0.5 micron technology.
• Using a package with more pins than the 40 bit
  used in MuP21 can expand to 32 bits instead of 20
  bits.
• Wider data/address bus improves throughput

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Next Generation MISC Chip

• F21 microprocessor
• Second generation VLSI design by Chuck Moore
  using OKAD.
• Fabricated in 0.8 micron CMOS technology using
  the HP process at Mosis.
• 68 pin PLCC package.
• More information, visit
• http//www.ultratechnology.com

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Conclusion

• MISC microprocessor is simpler and more efficient
  than RISC and CISC.
• Consumes less power when running at equivalent
  speed.
• MISC processor is cheaper than RISC and CISC in
  terms of price/performance ratio.