Class

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10-23-2007
(Lecture 18)
CS8421 Computing SystemsDr. Jose M. Garrido
Class Will Start Momentarily
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Addressing Modes

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

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Immediate Addressing

• Operand is part of instruction
• Operand address field
• e.g. ADD 5
• Add 5 to contents of accumulator
• 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

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Immediate Addressing Diagram
Instruction
Operand
Opcode
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Direct Addressing

• Address field contains address of operand
• Effective address (EA) address field (A)
• e.g. ADD A
• Add contents of cell A to accumulator
• Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
  address
• Limited address space

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Direct Addressing Diagram
Instruction
Address A
Opcode
Memory
Operand
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Indirect Addressing (1)

• Memory cell pointed to by address field contains
  the address of (pointer to) the operand
• EA (A)
• Look in A, find address (A) and look there for
  operand
• e.g. ADD (A)
• Add contents of cell pointed to by contents of A
  to accumulator

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Indirect Addressing (2)

• Large address space
• 2n where n word length
• May be nested, multilevel, cascaded
• e.g. EA (((A)))
• Multiple memory accesses to find operand
• Hence slower

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Indirect Addressing Diagram
Instruction
Address A
Opcode
Memory
Pointer to operand
Operand
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Register Addressing (1)

• Operand is held in register named in address
  filed
• EA R
• Limited number of registers
• Very small address field needed
• Shorter instructions
• Faster instruction fetch

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Register Addressing (2)

• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
• Requires good assembly programming or compiler
  writing
• In C programming
• register int a

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Register Addressing Diagram
Instruction
Register Address R
Opcode
Registers
Operand
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Register Indirect Addressing

• EA (R)
• Operand is in memory cell pointed to by contents
  of register R
• Large address space (2n)
• One fewer memory access than indirect addressing

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Register Indirect Addressing Diagram
Instruction
Register Address R
Opcode
Memory
Registers
Operand
Pointer to Operand
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Displacement Addressing

• EA A (R)
• Address field hold two values
• A base value
• R register that holds displacement or vice
  versa

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Displacement Addressing

• Common uses
• Relative addressing
• Base-register addressing
• Indexing

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Displacement Addressing Diagram
Instruction
Displacement A
Register R
Opcode
Memory
Registers
Pointer to Operand
Operand

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Relative Addressing

• A version of displacement addressing
• R Program counter, PC
• EA A (PC)
• i.e. get operand from A cells from current
  location pointed to by PC
• c.f locality of reference cache usage

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Base-Register Addressing

• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86

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Indexed Addressing

• A base
• R displacement
• EA A R
• Good for accessing arrays
• EA A R
• R

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Combinations

• Postindex
• EA (A) (R)
• Preindex
• EA (A(R))

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Stack Addressing

• Operand is (implicitly) on top of stack
• e.g.
• ADD Pop top two items from stack and add

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CPU Structure (Chapter 12)

• Requirements placed on the CPU
• Fetch instruction
• Interpret instruction
• Fetch data
• Process data
• Write data

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CPU With Systems Bus
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CPU Internal Structure
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Registers

• CPU must have some working space (temporary
  storage)
• These are called registers
• Number and function vary between processor
  designs
• One of the major design decisions
• Top level of memory hierarchy

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User Visible Registers

• General Purpose
• Data
• Address
• Condition Codes

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General Purpose Registers (1)

• May be true general purpose
• May be restricted
• May be used for data or addressing
• Data
• Accumulator
• Addressing
• Segment

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General Purpose Registers (2)

• Make them general purpose
• Increase flexibility and programmer options
• Increase instruction size complexity
• Make them specialized
• Smaller (faster) instructions
• Less flexibility

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How Many GP Registers?

• Between 8 - 32
• Fewer more memory references
• More does not reduce memory references and takes
  up processor real estate

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How Big Are the Registers?

• Large enough to hold full address
• Large enough to hold full word
• Often possible to combine two data registers
• C programming
• double int a
• long int a

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Condition Code Registers

• Sets of individual bits
• e.g. result of last operation was zero
• Can be read (implicitly) by programs
• e.g. Jump if zero
• Can not (usually) be set by programs

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Control Status Registers

• Program Counter
• Instruction Decoding Register
• Memory Address Register
• Memory Buffer Register
• Revision what do these all do?

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Program Status Word

• A set of bits
• Includes Condition Codes
• Sign of last result
• Zero
• Carry
• Equal
• Overflow
• Interrupt enable/disable
• Supervisor

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Other Registers

• May have registers pointing to
• Process control blocks (see O/S)
• Interrupt Vectors (see O/S)
• N.B. CPU design and operating system design are
  closely linked

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Example Register Organizations
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Instruction Cycle

• Includes the following subcycles
• Fetch
• Execute
• Interrupt

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The Indirect Cycle

• Can be thought of as additional instruction
  subcycle
• May require memory access to fetch operands
• Indirect addressing requires more memory accesses

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Instruction Cycle with Indirect
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Instruction Cycle State Diagram
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Data Flow (Instruction Fetch)

• Exact sequence of events of an instruction cycle
  depends on CPU design
• In general, during Fetch cycle
• PC contains address of next instruction
• Address moved to MAR
• Address placed on address bus
• Control unit requests memory read
• Result placed on data bus, copied to MBR, then to
  IR
• Meanwhile PC incremented by 1

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Data Flow (Data Fetch)

• IR is examined
• If indirect addressing, indirect cycle is
  performed
• Right most N bits of MBR transferred to MAR
• Control unit requests memory read
• Result (address of operand) moved to MBR

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Data Flow (Fetch Diagram)
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Data Flow (Indirect Diagram)
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Data Flow (Execute)

• May take many forms
• Depends on instruction being executed
• May include
• Memory read/write
• Input/Output
• Register transfers
• ALU operations

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Data Flow (Interrupt)

• Simple
• Predictable
• Current PC saved to allow resumption after
  interrupt
• Contents of PC copied to MBR
• Special memory location (e.g. stack pointer)
  loaded to MAR
• MBR written to memory
• PC loaded with address of interrupt handling
  routine
• Next instruction (first of interrupt handler) can
  be fetched

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Data Flow (Interrupt Diagram)
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Prefetch

• Fetch accessing main memory
• Execution usually does not access main memory
• Can fetch next instruction during execution of
  current instruction
• This operation is called instruction prefetch

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Improved Performance

• But not doubled
• Fetch usually shorter than execution
• Prefetch more than one instruction?
• Any jump or branch means that prefetched
  instructions are not the required instructions
• Add more stages to improve performance

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Pipelined Intructions

• While one instruction is being decoded, the next
  instruction is fetched
• While the first instruction is being executed,
  the second is decoded and the third is fetched.
• Overlapping the fetch, decode, and execute of
  several instructions allows programs to be
  executed more quickly.

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Pipelining

• To gain further speedup the pipeline, the
  following decomposition of the instruction
  processing is needed
• Fetch instruction
• Decode instruction
• Calculate operands (i.e. EAs)
• Fetch operands
• Execute instructions
• Write result

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Two Stage Instruction Pipeline
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Six Stage Instruction Pipeline
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Dealing with Branches

• Approaches
• Multiple streams
• Prefetch branch target
• Loop buffer
• Branch prediction
• Delayed branching

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Multiple Streams

• Have two pipelines
• Prefetch each branch into a separate pipeline
• Use appropriate pipeline
• Leads to bus register contention
• Multiple branches lead to further pipelines being
  needed

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Prefetch Branch Target

• Target of branch is prefetched in addition to
  instructions following branch
• Keep target until branch is executed
• Used by IBM 360/91

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Loop Buffer

• Very fast memory
• Maintained by fetch stage of pipeline
• Check buffer before fetching from memory
• Very good for small loops or jumps
• c.f. cache
• Used by CRAY-1

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Loop Buffer Diagram
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Branch Prediction (1)

• Predict never taken
• Assume that jump will not happen
• Always fetch next instruction
• 68020 VAX 11/780
• VAX will not prefetch after branch if a page
  fault would result (O/S v CPU design)
• Predict always taken
• Assume that jump will happen
• Always fetch target instruction

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Branch Prediction (2)

• Predict by Opcode
• Some instructions are more likely to result in a
  jump than thers
• Can get up to 75 success
• Taken/Not taken switch
• Based on previous history
• Good for loops

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Branch Prediction (3)

• Delayed Branch
• Do not take jump until you have to
• Rearrange instructions

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Branch Prediction Flowchart
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Branch Prediction State Diagram
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Supervisor Mode

• Intel ring zero
• Kernel mode
• Allows privileged instructions to execute
• Used by operating system
• Not available to user programs

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End of Lecture

• End
• Of
• Todays
• Lecture.
• 10-23-07