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More Hardware Logic

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Decode. Mux. Arith Logic Unit. Accumulator. Memory Data ... Instruction decoded. Operation code (What to do) Address of data in memory to use (if applicable) ... – PowerPoint PPT presentation

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Title: More Hardware Logic


1
More Hardware Logic
  • More Hardware Logic
  • NAND Gate
  • NOR Gate
  • Latch (Memory)
  • Computer Architecture
  • Processor Components
  • Fetch-Execute Cycles
  • Machine Language

2
NAND Gate
  • NAND NOT AND
  • Same as

0
1
0
1
1
1
1
0
3
NOR Gate
  • NOR NOT OR
  • Same as

0
1
0
1
0
1
0
0
4
Latch (Memory)
  • A latch can remember one binary digit
  • A group of latches is called a register
  • A register can store a binary value of a specific
    length in binary digits (bits)
  • Standard register sizes are
  • Eight bits ? One Byte
  • Sixteen bits ? One Word
  • Thirty two bits ? One Long Word

5
Logic for a Latch
  • A latch circuit (Corrected from Figure 7.15)

D Value of Bit To be stored
Q Value of Bit Remembered
G Gate Signal To Store/Hold
6
Try a latch with Logg-O
  • Go to AE On-Line Web Site
  • Go to Module 7
  • Go to Lab 7.4
  • Build and Test a Latch Circuit

7
Memory Cell
  • Based on Latch (Modified Figure 7.17)

Data In / Out
Read 0 Write 1
D
Q
Latch
G
Select
Modified here to work with our Latch circuit
8
Four Bit Register
  • Based on Four Memory Cells (Fig 7.18)

D0
D1
D2
D3
Read 1 Write 0
One Bit Memory Cell
One Bit Memory Cell
One Bit Memory Cell
One Bit Memory Cell
Address Selected
9
Computer Architecture
  • Processor Components

Data Bus
Instruction Register
Address
2
Mux
Decode
Program Counter
Arith Logic Unit
Accumulator
Memory Data and Instructions
10
Computer Architecture
  • Instruction Fetch
  • Program counter used as address to memory
  • Instruction fetched from memory
  • Instruction decoded
  • Operation code (What to do)
  • Address of data in memory to use (if applicable)
  • Instruction Execute
  • Data fetched from memory
  • Arithmetic or logic performed
  • Data stored in memory
  • Program counter updated

11
Computer Architecture
  • Machine Language Instructions
  • Portion of instruction is operation code
  • Portion of instruction may be immediate data
  • Portion of instruction may be memory address
  • Machine Language Instruction Format
  • Single word / multi-word instruction formats
  • Different bits in word(s) used for each field
  • Hard to program in binary code words!!
  • Leads to need for an assembly language

12
Computer Architecture
  • PIPPEN Machine / Assembly Language

Machine Language
Assembly Language
Direct Mode Operand
Direct Mode Operand
0000 CCCC AAAAAAAA
OPN A (A is an address)
Immediate Mode Operand
Immediate Mode Operand
0000 CCC0 NNNNNNNN
OPN N (N is a number)
No Operand
No Operand
OPN
0000 CCC0 --- unused ---
13
Computer Architecture
  • Look at Computer Simulation
  • Go to AE On-Line Web Site
  • Go to Module 7
  • Go to Lab 7.5
  • Starting with this in Module 6 next time
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