CSECE 365 COMPUTER ARCHITECTURE

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CS/ECE 365 COMPUTER ARCHITECTURE

• SOUNDARARAJAN EZEKIEL
• DEPARTMENT OF COMPUTER SCIENCE
• OHIO NORTHERN UNIVERSITY

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Datapath and control Introduction

• We did performance of a machine
• 3 factors--- instruction count---clock cycle
  time--and clock cycles per instruction(CPI)
• CPU time ICCPIClock cycle time
• clock cycle time 1/clock rate
• Clock cycle time Hardware technology and
  organization
• CPI Organization and instruction set
  architecture
• Instruction count Instruction set architecture
  and compiler technology

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continue

• We will discuss datapath and control unit for two
  different implementation of the MIPS instruction
  set
• which includes
• Memory -reference instructions load word (lw)
  and store word(sw)
• Arithmetical-Logical Instruction add, sub, and
  , or, slt
• The instructions branch equal (beq) and jump (j)

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Five Clock Cycles

• Instruction Fetch cycle(IF)
• Instruction decode/register fetch cycle(ID)
• Execution (EX)
• Memory Access(MEM)
• Write-Back Cycle(WB)

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Notes

• A given ISA may be implemented with different
  ways
• Example Intel Pentium ISA has been implemented
  in different ways, all of which support the same
  ISA
• Not only Intel, number of competitors --AMD,
  Cyrix have implemented Pentium ISA

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Basic of Architecture

• The functionality of the architecture centers
  around the fetch-execute cycle, which is in some
  sense the heart of the machine
• 1. Fetch the next instruction to be executed from
  memory
• 2. Decode the opcode(specify the operation to be
  performed)
• 3. Read operand(s) from main memory or registers
  if any
• 4. Execute the instruction and store results
• 5. Go to step 1

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• An architecture consists of a data section, which
  contains registers and an ALU and a control
  section
• The data section is also referred as datapath

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High level view of a architecture
CONTROL UNIT
Registers
ALU
Data path (data section)
Control section
SYSTEM BUS
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MIPS major functional unit and the connections
Address Instruction Instruction Memory
DATA Registers
ALU
PC
ADDRESS DATA
DATA MEMORY
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• send the program counter to memory that contain
  code and fetch the instruction from that memory
• read 1 or 2 registers, using fields of
  instructions to select the register to read for
  lw we need 1 register, most others need
  2-registers
• uses ALU
• memory reference instruction address
  calcualtion
• alu instruction operation execution
• branches comparisons

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• after ALU
• memory-ref instruction--- access memory either
  write for store or read data for load
• alu instruction-- must write data back to
  registers
• branch ins--- need to change the instruction
  according based on comparison

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Logic Design

• functional units in MIPS implementation consists
  of 2 different type logic elements
• combinational outputs are depends only on the
  current inputs
• given the same input, combinational element
  always produce the same output
• ALU-- MIPS functional is combinational --- there
  is no internal storage

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• State an element contain state that means it
  has some internal storage
• we call these elements are state elements
• Instruction, data memory, and all registers are
  state elemets
• if we pull the plug, we can restart the computer
  by using the information stored before we pull
  the plug

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• State 2 input one output--
• INPUT 1.data value to be written into the
  element-- 2. clock (determine when the date value
  is written)
• OUTPUTprovides the value that was written in an
  earlier clock cycle
• example memories, and registers-- clock is used
  to determine when the state element should be
  written-- state element can be read at any time

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sequential

• logic components that contains state are also
  called sequential because their outputs depend on
  both their inputs and the contents of the
  internal state

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Clocking methodology

• It defines when the signal can be read and when
  they can be written
• time is important because if a signal is
  written at the same time it is read, the value of
  read could be old value-- or mixed values--
• clocking methodology is to designed to prevent
  this problem

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edge-triggered clocking methodology

• any values stored in the machine are updated only
  on a clock edge. gt state elements all update
  their internal storage on the clock edge
• following slide shows --2 state elements --
  surrounding a block of combinational logic--
  which operate on a single clock cycle
• all three stages in one single clock cycle

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Combinational Logic
State element 1
State element 2
Clock cycle
Combinational logic, state elements, and the
clock are closely related
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Note

• not showing write control signal when the state
  element is written on every active clock edge
• if state is not updated every clock-- we need
  write control signal --- this case both the clock
  cycle and write control signal are input--state
  element will change only if write control signal
  is asserted and clock edge occurs

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• an edge-triggered methodology allows us to read
  the contents of a register, send the value
  through some combinational logic, and write that
  registers in the same clock cycle

Combinational logic
State ele
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Note

• nearly all of these state and logic elements are
  32 bit input and output( that is the data handle
  by the processor)
• building datapath
• simple/multicycle implementation
• microprgramming
• CAD--application
• use datapath for pipelining