Midterm Review

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Midterm Review
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68000 INTERFACE CONTD
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System Support Pins RESET, HALT, CLOCK

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Bus Arbitration Control Handshaking
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Bus Arbitration Control
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Interrupt Control Interface
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Synchronous Bus Control
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68000 Read Cycle, Timing Diagram
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68000 Read Cycle, Timing Parameters
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68000 Write Cycle, Timing Diagram
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Memory Timing Parameters
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Is Memory Fast Enough?
3tcyc gt tCLAV tAA tDICL ?
tAA lt 3125 70 15 290 ns
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Is the data bus cleared in time?
62.5 ns
130 ns
tCLSH t2 tCHZ 70 10 50 130 ns
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Bus Contention in a Read Cycle
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Full Address Decoding Example

• 2 K-words of ROM1
• 8 K-words of ROM2
• 2 K-words of RAM
• 2 Words of PERI1
• 2 Words of PERI2

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Full Address Decoding Table
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Full Address Decoding Example (Contd)
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Partial Address Decoding Example

• 2 K-words of ROM1
• 8 K-words of ROM2
• 2 K-words of RAM
• 2 Words of PERI1
• 2 Words of PERI2

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Partial Address Decoding Table
Note blank entries are address lines not used in
decoding
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Partial Address Decoding Example (Contd)
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The 74LS138 3-line-to-8-line Decoder

• 0100 0000 0000 0000 0000 0000
• - 0111 1111 1111 1111 1111 1111
• - OR
• 400000 7FFFFF

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The 74LS138 3-line-to-8-line Decoder

• 0010 0000 0000 0000 0000 0000 - 0011 1111
  1111 1111 1111 1111
• - OR
• 200000 3FFFFF

18-bits select memory range 218 256K bytes
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Memory Organizations

• 16 chips of 4M x 1-bit

8 chips of 256K x 8-bits