The previous section introduced the general concepts

1
The previous section introduced the general
concepts of the microprocessor. The
microprocessor is the central component to a
computer system. It connects to both memory
and I/O by buses. The are three types of Bus
Address , Data and Control and these were
discussed in the last section The microprocessor
operates under stored program
2
The program is stored in memory in binary
numbers. These binary numbers represent
instructions which the microprocessor is to
execute. The microprocessor fetches the
instructions from memory, decodes what the
instruction is and then before executing the
instruction completes any additional operates
which make up the particular operation
required.Having completing this phase the
instruction is executed. This is called FETCH,
DECODE , EXECUTE CYCLE.
3
The internal architecture of a microprocessor is
quite complicated. However, the fundamental
operation of the MPU is the Fetch,Decode, Execute
Cycle. The internal architecture of the MPU will
now be presented.This initial presentation is a
somewhat simplified version of a real MPU,
however the main elements, which are common to
most MPU architectures, will covered. Before
presenting the MPU internal architecture, few
basics regarding the size of buses, and some
simplified bus timing diagrams.
4
Bus Sizes Buses are specified in width, number
of bits. There are other parameters which can
also used to characterise a Bus but for this
presentation they are not relevant.
5
Address Bus The MPU Address bus size specifies
how much memory and I/O locations may
accessed. Number of locations 2N where N is
number of Address lines The Address Bus may be
specified using the following 16 Bits Wide, (
A15 to A0 ), 16 Address Lines In this instance
2N 216 65536 locations
6
The Address Range starts at 0 and ends at a
maximum 65535. Notice that the highest address
location is one less than the Number of locations
given by 2N . This is due to the number 0 being
a valid memory location. Addresses are general
expressed in the Hexadecimal numbering system.
Which will be covered later. This number system
is base 16. So that a typical 16 bit address will
use values such as 1234H or 123416 or FFFFH or
FFFF16 more later.
7
The Data Bus is similarly characterised by its
width, number of bits. The width of the external
Data bus generally gives a very good indication
of the internal MPU architecture, particularly
the registers size and the ALU. However, there
are exceptions The Data Bus width limits the
bandwidth of the data that can be transferred
per bus operation. Data Bus 8 Bits , tends to
represent a 8 bit internal architecture.
8
The Control Bus is made up with several different
signals The control signals on the MPU also tend
to hint at the internal architecture of the MPU
in terms of how it treats memory and I/O. More
Details on this later.
9
Simple Bus Timing Diagrams. The timing diagrams
attempt to show the sequence of events over time
on the Three MPU Buses. To Read a timing diagram
, time 0 generally starts on the left hand side,
with time increasing to the right. The timing
diagram is indicative only.
10
Hi Z means High Impedance or floating bus /
signal. VALID INFO means either a group of BUS
signals or an individual signal is Stable at this
time.
11
(No Transcript)
12
Simple Read Cycle 1. Address onto Address Bus 2.
READ (RD) Control Signal Asserted by MPU 3. Data
Placed from Memory onto the Data Bus 4. RD signal
De-Asserted, Data into MPU temp register. 5. Read
Cycle Ends
13
(No Transcript)
14
Write Cycle 1. Address placed on ADDRESS BUS 2.
Data placed onto DATA BUS 3. Write (WR) Control
Signal Asserted by MPU 4. Write (WR) Control
Signal De-Asserted and Data Written into
Memory 5. Write Cycles completes.
15
Microprocessor Architecture The microprocessor
architecture refers to the internal structure or
organization of a MPU and show how its internal
subsystems interact and how they are linked
together. The previous sections have looked at
the external computer system and its components.
The next section will delve into the internals of
the MPU. You will note that the internal MPU
structure have some of the same features of the
external computer for instance an
internal bus structure.
16
The MPU architectural features can be divided
into several categories. The MPU architecture
can be viewed both externally or internally.
(They might not be the same) The MPU
architecture refers to both its Hardware and
Software features which are referred to as
Models.
17
MPU Hardware Model includes MPU Register Set
Numbers of Registers MPU Data width
8Bit, 16Bit, 32 Bit Address Bus width Number
of Addressable locations Control Signals
Types
18
SOFTWARE MODEL includes Instruction Set
Addressing Modes Linked with the Instruction
Set
19
The majority of all 8 Bit MPU implement the
same standard architecture. The two chief
functions of any processor are processing and
control. A simplified model of a MPU consists
of 1. Registers (Temporary Storage) 2. The
Arithmetic Logic Unit (ALU) 3. Control
Circuits All with work together to form the MPU
20
REGISTER CAN BE ACCESSED 16 BIT E.G. LD BC,1234
REGISTER CAN BE ACCESSED 8 BIT E.G. LD B,0
MPU REGISTER SET
NOTE NUMBER ARE BASE 16 HEX 123416
21
Registers The MPU contains a number of different
registers that provide storage for multi-bit data
during processing. Each register is a group of
memory cells used to provide temporary storage
of words(binary values) within a MPU. Each cell
is a flip-flop that can store one bit of
information. When flip-flops are organised to
store a binary word, the arrangement is referred
to as a register. A counter is a register,
organised such that each clock pulse
causes the contents of the register to be
incremented by one
22
Register Group of D type Flip-flops
Controlled transfer of data from inputs to outputs
23
The Register includes the Program Counter
(PC) which is central how the MPU keeps track of
where it is within the program. More details to
follow...
24
ACCUMULATOR REGISTER
FLAGS REGISTER (STATUS REGISTER)
TMP1 2 TEMPORARY REGISTERS
ARITHMETIC LOGIC UNIT
25
Arithmetic Logic Unit (ALU) The ALU is made up
of logic circuits whose function is to process
data. MPU are typically classified as 4,8,16 or
32 bit processors according to the number of bits
that be simultaneously processed. The of bits
that can be processed simultaneously is
determined by the number of binary adder
circuits in the ALU. (Parallel binary adder
chain)
26
The ALU is responsible for carrying out
arithmetic and logical operations involving its
two inputs Arithmetic and Logic processes almost
always involve processing two numbers( or
operands). Eg. Addition and subtraction of two
numbers. Therefore the ALU in a 8 Bit MPU has two
8 bit input ports, one for each operand An 8 Bit
MPU performs operations between two 8 Bit
numbers and delivers a corresponding result.
27
The type of functions performed by the ALUs of
MPU include Addition
Shift Left Subtraction
Shift Right Logical AND
Decrement Logical OR
Increment Logical XOR
28
The basic function as stated is to perform logic
and maths operations. The Accumulator and the
Flags registers play an important role in the
operation of the ALU. The Accumulator is used
in all ALU operations. The Flags or Status
Register is a group of bits representing the
result of the ALU operation. The Flags register
contains bits such as OV representing an overflow
flag. If the result of an addition is greater
than 255 then the OV is set to indicate
this condition. More Details to come.
29
IDU
IR Instruction Register DATA -gt IR IR -gt
IDU Control Signals generated
30
The MPU Control Circuitry As stated previously a
MPU program is a sequence of binary values held
in memory. These binary values represent instructi
ons to the MPU. The instructions tell the MPU
what to do. The MPU control circuitry consists
of the Instruction Register (IR) and the
Instruction Decoder Unit (IDU).
31
The Instruction Register When a instruction is
read from memory, the contents from the memory
are placed in the IR. The IR passes its contents
to the IDU. IR register can only contain an
instruction and is therefore only accessed
during a instruction fetch cycle (opcode read
from memory).
32
The Instruction Decode Unit The IDU is central
the operation of the MPU. The IDU function is
to read the IR contents and then decode /
interpret the data to find out which operation is
required. The IDU then completes the
instruction by completing the decode and
execution phases of the fetch decode execute
cycle. These phases result in many internal
and external control signals sequences being
generated to achieve the required operation.
33
The IDU is responsible for generating both the
internal and external control signals. These
signals occur in a specific order or sequence at
a particular timing interval. The internal
control signals manage the internal
switches which control the flow of data ( routing
of data) throughout the MPU The external
control signals are generated by the IDU
to co-ordinate the access of and the synchronised
of data exchange with the external system
components, memory and I/O. Typically External
Read / Write Bus Accesses.
34
The Instruction Decode Unit , sometimes called
the Control Unit. Can be implement in two
ways Hardwired Logic Microcode (micro
sequencer)
35
Hardwired Logic Hardwired Logic is where the
binary pattern in the IR directly drives the
input to a combinational and / or sequential
logic block which generates all the
required internal and external control signals.
36
Microcode Microcode are small sequences
micro-instructions which are executed in the IDU.
Each MPU instruction is made up several of
these lower level micro-instructions which when
are executed generate the correct internal and
external control signals to complete the current
instruction. Each instruction will have a unique
sequence of micro-instructions.
37
(No Transcript)
38
(No Transcript)
39
(No Transcript)
40
(No Transcript)
41
(No Transcript)
42
(No Transcript)
43
(No Transcript)
44
(No Transcript)
45
(No Transcript)
46
(No Transcript)
47
(No Transcript)
48
(No Transcript)
49
(No Transcript)
50
(No Transcript)
51
(No Transcript)
52
(No Transcript)
53
(No Transcript)
54
(No Transcript)
55
(No Transcript)