68HC11 External Memory Expansion

1
68HC11 External Memory Expansion
Address space assignment Address decoding Timing
considerations
2
Memory Space Assignments

• Port B gt A15-A8
• Port C gt A7/D7 A0/D0
• 16 bits address lines gt 216 64KB space
• 68HC11A8 on-chip memory map
• 0000 -00FF on-chip SRAM
• 1000 -103F I/O registers
• B600 -B7FF on-chip EEPROM
• E000 -EFFF on-chip ROM
• Can the on-chip memory map be changed?

3
Rearrange SRAM I/O registers memory space

• By programming the INIT register, located at
  103D
• Reset value of the INIT register

RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
1
RAM3-RAM0 control the RAM map position
REG3-REG0 control the 64-byte register block
position
4
SRAM position
4KB 212 KB
F000
256 bytes
4KB 212 KB
E000
256 bytes
4KB 212 KB
RAM3
RAM2
RAM1
RAM0
D000
256 bytes
x
x
x
x
RAM3-RAM0 control the RAM map position
4KB 212 KB
256 bytes
2000
4KB 212 KB
1000
256 bytes
4KB 212 KB
0000
256 bytes
5
64-byte register block position
64 bytes
4KB 212 KB
F000
4KB 212 KB
E000
REG3
REG2
REG1
REG0
4KB 212 KB
0
0
0
1
D000
REG3-REG0 control the 64-byte register block
position
4KB 212 KB
2000
4KB 212 KB
1000
4KB 212 KB
0000
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Overlapping Issues

• Priority
• Internal I/O register gt RAM gt ROM
• Internal gt external
• Exercise 5.2 Remap SRAM to 2000-20FF and I/O
  registers to 3000 - 303F
• Understand the code in the text

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EVBU Memory Map (page102)
SRAM
0000 - 01FF
0200- 0FFF
I/O registers
1000- 103F
1040 - B5FF
Memory Space forExternal devices
EEPROM
B600 - B7FF
B800 - CFFF
ROM
D000 - FFFF
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Address DecodingBasic Concept
HC11
To transfer data correctly and protect the
computer from damaging, only one device at a
time should be allowed to drive the data bus.The
address decoder selects and enables one and only
one data transfer device at a time.
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74138 74139 decoder
74138
O0
E1
O1
E2
74139
1Y0
E1
O2
E3
1Y1
A1
O3
1Y2
A0
O4
A2
1Y3
O5
2Y0
A1
O6
E2
2Y1
O7
A0
B1
2Y2
B0
2Y3
3-to-8 decoder
2-to-4 decoder
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Example 5.5Full Address Decoding

• SRAM1 2000 - 3FFF
• ROM1 4000 - 5FFF
• EEPROM 6000 - 7FFF
• SRAM2 A000 - BFFF
• ROM2 C000 - DFFF

SRAM1
ROM1
HC11
Address bus
Data bus
Control bus
SRAM2
ROM2
EEPROM
Address decoding circuit
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Thinking process

• How big (in size) is each memory device?
• How many chunks are needed in the 64KB address
  space?
• What is the address space for each device?
• Which bits can be used to select the device,
  i.e., those bits that are unique enough?
• How do you apply the 74138 in this case?
• How do you connect all the address lines among
  the HC11, the address decoder, and the devices?
• Why is this scheme called fully address
  decoding?

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Example 5.6Partial Address Decoding

• Product information 2KB (211) external EEPROM
  and 2KB external SRAM

HC11
Address bus
Data bus
Control bus

• The lowest 11 address bits are connected
  directly to the memory devices address pins
• The highest 5 bits are available for address
  decoder
• However, we dont need to use all 5 bits.
• The example only uses 2 bits A15 and A14
• 74LS139 is used (2-to-4 decoder)

SRAM
EEPROM
Why is this partial address decoding? Whats
good about it? Whats bad about it?
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Multilevel decoding (Exp 5.7)

• 2 x 8KB SRAM
• 2 x 8KB EPROM
• 1 x 8KB flash memory
• 8 x I/O devices (usually I/O devices have fewer
  registers in this example, 40016 1024 1KB
  address spaces are reserved for each I/O device)
• Totally 13 devices need to be supported.
  However, 74138 can only generates up to 8 control
  signals.
• The solution multilevel decoding
• Design issues (a) Space allocation (b) address
  pins selection (A13, A14, A15 for 8KB devices,
  A10, A11, A12 for 1KB I/O devices)

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Exp 5.7
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How to read timing charts?

• Single-signal waveform, multiple-signal waveform
  (Fig. 5.7, 5.8)
• Unknown signals (Fig. 5.9)
• Floating (not driven) signals (Fig. 5.10)
• Causal relationships between signals (Fig. 5.11)

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Bus Cycles

• MC68HC11 Read bus cycle (Fig. 5.12.)
• MC68HC11 Write bus cycle (Fig. 5.13)
• HM6264A Read cycle timing diagram (Fig. 5.15)
• HM6264A Write cycle timing diagram (Fig. 5.16)

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Interfacing Design

• Fig. 5.17, interfacing an 8KB HM6264A to 68HC11
• Fig. 5.18, overlapped 68HC11 and HM6264A read
  cycle timing diagram
• Fig. 5.19, overlapped 68HC11 and HM6264A write
  cycle timing diagram