DORIC Status

1
DORIC Status

• Amir Rahimi
• The Ohio State University

February 16, 2004
K. Arms, K.K. Gan, M.O. Johnson, H.P. Kagan, R.D.
Kass, A. Rahimi, C. Rush, R. Ter-Antonian, M.
Zoeller The Ohio State University P. Buchholz,
A. Coilox, M. Holder, S. Nderitu, A. Niculae, M.
Ziolkowski Siegen University
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Outline

• DORIC Specifications
• Design History
• Irradiation Results
• Summary

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Digital Optical Receiver IC Specs

• l Decode Bi-Phase Mark encoded (BPM) clock and
  command
• signals from PIN diode
• l Input signal step size
• 90 mA to 1100 mA
• l Extract 40MHz clock
• l Duty cycle (50 4)
• l Total timing error lt 1ns
• l Bit Error Rate (BER)
• lt 10-11 at end of life
• Compatible with common
• cathode PIN array

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DORIC Logic
l Training period 1ms (incl. Reset)
40MHz Recovered Clock
Delay of Trailing Edges
Delay Locked Loop Duty Cycle 50 ?
Ready for data
BPM
Recovered Data
Recovered 40MHz Clock
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DORIC Design History

• Original design by ATLAS SemiConductor Tracker
  (SCT) team
• AMS 0.8 mm BiPolar in radiation tolerant
  process, 4 V supply voltage
• DMILL 0.8mm CMOS, radiation hard with 3.2 V
  supply voltage,
• 3 submissions Summer 1999 - May 2001.
• 3 meets original electrical specs
• but severe degradation of circuit performance in
  April 2001 Irradiation!
• Not radiation hard enough for ATLAS pixel optical
  link!
• Migrate to IBM 0.25mm early 2001, 2.5 V
• Enclosed layout transistors and guard rings for
  improved radiation hardness
• Five submissions Feb 2001 March 2003
• To date over 30 DORIC-I5e chips have been tested
• 18 chips on opto-boards
• 16 chips on test boards

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DORIC Digital Circuitry

• edgedet produces pulses for each input
  transition
• clock recovery circuit uses delay-locked-loop,
  consisting of dcontrol and three internal voltage
  controlled delays, dflip1 and exor circuits
• data recovery circuit latches the state of the
  recovered clock into dfilp2 using edgedet signal

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Timing of Digital Signals
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DORIC-I5e Layout 2.3 X 4.0 mm
Preamp / Digital Test Pads
Output Pads Dat Dat- Clk Clk- GndD VddD
Input Pads Signal_in GndA Noise_in VddAmp VddA
Analog / Digital Bias, Resets
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Irradiation of DORIC-I5e, August 2003

• 24 GeV proton test beam at CERN (T7)
• Cold box electrical testing of 4-channel DORIC
  and VDC
• Up to 62 Mrad
• Shuttle testing of optical links on opto-board
  using DORIC and VDC
• Up to 30 Mrad

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Rise/Fall times

• Rise/Fall time

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Clock Jitter, Command-Clock Delay and Duty Cycle

• Jitter ( lt 1 ns)
• Command delay wrt. clock
• Duty Cycle slightly out of spec after irradiation
• Min 45.5 (50 4)
• Measured on the test board, close to 50 on
  opto-board

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LVDS (/-) Amplitude, Average
After irrad.
Before irrad.

• (?) Clock Average/Amplitude slightly out of
  spec after irradiation
• Max Average 0.51 V (spec 0.2 - 0.5)
• Max Amplitude 1.52 V (spec 1.0 - 1.5)

• Command Average/Amplitude

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Single Event Upset Error Rate
OSU
Siegen

• Bit error decreases with increasing PIN current
• Fexpect 2 x 106 cm-2 s-1, IPIN 100mA BER 3
  x 10-10
• DORIC Spec 10 -11

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PIN Current Threshold vs. Dosage

• PIN Current threshold for no bit error remain
  constant

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Summary

• DORIC-I5e meets all the specifications
• Radiation hardness of DORIC-I5e is adequate for
  the Pixel system
• Circuits continue to perform well after up to 62
  Mrad of 24 GeV protons