PRS for Kishores lecture for Jan 26, 2006

1
PRS for Kishores lecture for Jan 26, 2006
2
input
register
clock
register
clock
register
clock
output

• Q1. (30 secs) How many clock cycles are needed to
  get the value at the input to the output in the
  above picture
• 0 cycles
• 1 cycles
• 2 cycles
• 3 cycles
• 4 cycles

3

• Q2. (30 secs) A bus is good idea for connecting
  datapath elements because
• It makes the CPU faster
• It reduces the number of wires and hence the
  complexity of the design
• It gives connectivity for all the datapath
  elements
• Kishore said so!
• Is a bus the same as a trolley?

4

• Q3. (30 secs) A and B registers in the datapath
  of LC-2200-8 are there because
• It is a good idea to buffer the inputs to the ALU
• There is a single bus in the datapath
• ALU is slow
• These registers are needed in the instruction-set
  architecture
• Kishore knows his alphabets

5

• Q4. (30 sec) FSM
• Is an abstract representation of the control unit
  of the processor
• Is a particular instruction in the
  instruction-set of LC-2200
• Is another name for ROM
• Is another name for PLA
• Is the way control bits are assigned in the words
  of the ROM
• None of the above

6
LdA
LdB
LdC
Assume initially A 32 B 456 C 789
A
B
C
0

• Q5. (30 sec) In the above circuit if LdA, LdB,
  and LdC are enabled in a clock cycle, then in the
  next clock cycle the contents of the registers
• A B C 0
• A 0 B C 32
• A 0 B 32 C 456
• A 789 B 32 C 456
• No change