EECS 252 Graduate Computer Architecture Lecture 2 0 Review of Instruction Sets, Pipelines, and Cache

1
EECS 252 Graduate Computer ArchitectureLecture
2 ?0 Review of Instruction Sets, Pipelines,
and Caches

• John Kubiatowicz
• Electrical Engineering and Computer Sciences
• University of California, Berkeley
• http//www.eecs.berkeley.edu/kubitron/cs252
• http//www-inst.eecs.berkeley.edu/cs252

2
Review Amdahls Law
Best you could ever hope to do
3
Review Computer Performance
CPI
inst count
Cycle time

• Inst Count CPI Clock Rate
• Program X
• Compiler X (X)
• Inst. Set. X X
• Organization X X
• Technology X

4
Today Quick review of everything you should
have learned ?0( A countably-infinite set of
computer architecture concepts )
5
Cycles Per Instruction (Throughput)
Average Cycles per Instruction
CPI (CPU Time Clock Rate) / Instruction Count
Cycles / Instruction Count
Instruction Frequency
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Example Calculating CPI bottom up
Run benchmark and collect workload
characterization (simulate, machine counters, or
sampling)
Base Machine (Reg / Reg) Op Freq Cycles CPI(i) (
Time) ALU 50 1 .5 (33) Load 20 2
.4 (27) Store 10 2 .2 (13) Branch 20 2
.4 (27) 1.5
Typical Mix of instruction types in program
Design guideline Make the common case fast MIPS
1 rule only consider adding an instruction of
it is shown to add 1 performance improvement on
reasonable benchmarks.
7
Definition Performance

• Performance is in units of things per sec
• bigger is better
• If we are primarily concerned with response time
• X is n times faster than Y means

8
ISA Implementation Review
9
A "Typical" RISC ISA

• 32-bit fixed format instruction (3 formats)
• 32 32-bit GPR (R0 contains zero, DP take pair)
• 3-address, reg-reg arithmetic instruction
• Single address mode for load/store base
  displacement
• no indirection
• Simple branch conditions
• Delayed branch

see SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM
PowerPC, CDC 6600, CDC 7600, Cray-1,
Cray-2, Cray-3
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Example MIPS ( MIPS)
Register-Register
5
6
10
11
31
26
0
15
16
20
21
25
Op
Rs1
Rs2
Rd
Opx
Register-Immediate
31
26
0
15
16
20
21
25
immediate
Op
Rs1
Rd
Branch
31
26
0
15
16
20
21
25
immediate
Op
Rs1
Rs2/Opx
Jump / Call
31
26
0
25
target
Op
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Datapath vs Control
Datapath
Controller
Control Points

• Datapath Storage, FU, interconnect sufficient to
  perform the desired functions
• Inputs are Control Points
• Outputs are signals
• Controller State machine to orchestrate
  operation on the data path
• Based on desired function and signals

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5 Steps of MIPS DatapathFigure A.2, Page A-8
Memory Access
Instruction Fetch
Instr. Decode Reg. Fetch
Execute Addr. Calc
Write Back
Next PC
MUX
Next SEQ PC
Zero?
RS1
Reg File
MUX
RS2
Memory
Data Memory
L M D
RD
MUX
MUX
Sign Extend
IR lt memPC PC lt PC 4
Imm
WB Data
RegIRrd lt RegIRrs opIRop RegIRrt
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Simple Pipelining Review
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5 Steps of MIPS DatapathFigure A.3, Page A-9
Memory Access
Instruction Fetch
Execute Addr. Calc
Write Back
Instr. Decode Reg. Fetch
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
IR lt memPC PC lt PC 4
Sign Extend
WB Data
Imm
A lt RegIRrs B lt RegIRrt
RD
RD
RD
rslt lt A opIRop B
WB lt rslt

• Data stationary control
• local decode for each instruction phase /
  pipeline stage

RegIRrd lt WB
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Visualizing PipeliningFigure A.2, Page A-8
Time (clock cycles)
I n s t r. O r d e r
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Pipelining is not quite that easy!

• Limits to pipelining Hazards prevent next
  instruction from executing during its designated
  clock cycle
• Structural hazards HW cannot support this
  combination of instructions (single person to
  fold and put clothes away)
• Data hazards Instruction depends on result of
  prior instruction still in the pipeline (missing
  sock)
• Control hazards Caused by delay between the
  fetching of instructions and decisions about
  changes in control flow (branches and jumps).

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One Memory Port/Structural HazardsFigure A.4,
Page A-14
Time (clock cycles)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 6
Cycle 7
Cycle 5
I n s t r. O r d e r
Load
DMem
Instr 1
Instr 2
Instr 3
Ifetch
Instr 4
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One Memory Port/Structural Hazards(Similar to
Figure A.5, Page A-15)
Time (clock cycles)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 6
Cycle 7
Cycle 5
I n s t r. O r d e r
Load
DMem
Instr 1
Instr 2
Stall
Instr 3
How do you bubble the pipe?
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Speed Up Equation for Pipelining
For simple RISC pipeline, CPI 1
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Example Dual-port vs. Single-port

• Machine A Dual ported memory (Harvard
  Architecture)
• Machine B Single ported memory, but its
  pipelined implementation has a 1.05 times faster
  clock rate
• Ideal CPI 1 for both
• Loads are 40 of instructions executed
• SpeedUpA Pipeline Depth/(1 0) x
  (clockunpipe/clockpipe)
• Pipeline Depth
• SpeedUpB Pipeline Depth/(1 0.4 x 1) x
  (clockunpipe/(clockunpipe / 1.05)
• (Pipeline Depth/1.4) x
  1.05
• 0.75 x Pipeline Depth
• SpeedUpA / SpeedUpB Pipeline Depth/(0.75 x
  Pipeline Depth) 1.33
• Machine A is 1.33 times faster

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CS 252 Administrivia

• Sign up! Web site is (doesnt quite work!)
  http//www.cs.berkeley.edu/kubitron/cs252
• In class exam on Wednesday January 24th
• Improve 252 experience if recapture common
  background
• Bring 1 sheet of paper with notes on both sides
• Doesnt affect grade, only admission into class
• 2 grades Admitted or audit/take CS 152 1st
  (before class Friday)
• Review Chapter 1, Appendix A, CS 152 home page,
  maybe Computer Organization and Design
  (COD)2/e
• If did take a class, be sure COD Chapters 2, 5,
  6, 7 are familiar
• Copies in Bechtel Library on 2-hour reserve

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CS 252 Administrivia

• Resources for course on web site
• Check out the ISCA (International Symposium on
  Computer Architecture) 25th year retrospective on
  web site.Look for Additional reading below
  text-book description
• Pointers to previous CS152 exams and resources
• Lots of old CS252 material
• Interesting links. Check out the WWW Computer
  Architecture Home Page
• Size of class seems ok
• I asked Michael David to put everyone on waitlist
  into class
• Check to make sure

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Data Hazard on R1Figure A.6, Page A-17
Time (clock cycles)
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Three Generic Data Hazards

• Read After Write (RAW) InstrJ tries to read
  operand before InstrI writes it
• Caused by a Dependence (in compiler
  nomenclature). This hazard results from an
  actual need for communication.

I add r1,r2,r3 J sub r4,r1,r3
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Three Generic Data Hazards

• Write After Read (WAR) InstrJ writes operand
  before InstrI reads it
• Called an anti-dependence by compiler
  writers.This results from reuse of the name
  r1.
• Cant happen in MIPS 5 stage pipeline because
• All instructions take 5 stages, and
• Reads are always in stage 2, and
• Writes are always in stage 5

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Three Generic Data Hazards

• Write After Write (WAW) InstrJ writes operand
  before InstrI writes it.
• Called an output dependence by compiler
  writersThis also results from the reuse of name
  r1.
• Cant happen in MIPS 5 stage pipeline because
• All instructions take 5 stages, and
• Writes are always in stage 5
• Will see WAR and WAW in more complicated pipes

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Forwarding to Avoid Data HazardFigure A.7, Page
A-19
Time (clock cycles)
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HW Change for ForwardingFigure A.23, Page A-37
MEM/WR
ID/EX
EX/MEM
NextPC
mux
Registers
Data Memory
mux
mux
Immediate
What circuit detects and resolves this hazard?
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Forwarding to Avoid LW-SW Data HazardFigure A.8,
Page A-20
Time (clock cycles)
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Data Hazard Even with ForwardingFigure A.9, Page
A-21
Time (clock cycles)
I n s t r. O r d e r
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Data Hazard Even with Forwarding(Similar to
Figure A.10, Page A-21)
Time (clock cycles)
lw r1, 0(r2)
I n s t r. O r d e r
sub r4,r1,r6
and r6,r1,r7
Bubble
ALU
DMem
or r8,r1,r9
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Software Scheduling to Avoid Load Hazards
Try producing fast code for a b c d e
f assuming a, b, c, d ,e, and f in memory.
Slow code LW Rb,b LW Rc,c ADD
Ra,Rb,Rc SW a,Ra LW Re,e LW
Rf,f SUB Rd,Re,Rf SW d,Rd

• Fast code
• LW Rb,b
• LW Rc,c
• LW Re,e
• ADD Ra,Rb,Rc
• LW Rf,f
• SW a,Ra
• SUB Rd,Re,Rf
• SW d,Rd

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Control Hazard on BranchesThree Stage Stall
What do you do with the 3 instructions in
between? How do you do it? Where is the commit?
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Branch Stall Impact

• If CPI 1, 30 branch, Stall 3 cycles gt new
  CPI 1.9!
• Two part solution
• Determine branch taken or not sooner, AND
• Compute taken branch address earlier
• MIPS branch tests if register 0 or ? 0
• MIPS Solution
• Move Zero test to ID/RF stage
• Adder to calculate new PC in ID/RF stage
• 1 clock cycle penalty for branch versus 3

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Pipelined MIPS DatapathFigure A.24, page A-38
Memory Access
Instruction Fetch
Execute Addr. Calc
Write Back
Instr. Decode Reg. Fetch
Next SEQ PC
Next PC
MUX
Adder
Zero?
RS1
Reg File
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
WB Data
Imm
RD
RD
RD

• Interplay of instruction set design and cycle
  time.

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Four Branch Hazard Alternatives

• 1 Stall until branch direction is clear
• 2 Predict Branch Not Taken
• Execute successor instructions in sequence
• Squash instructions in pipeline if branch
  actually taken
• Advantage of late pipeline state update
• 47 MIPS branches not taken on average
• PC4 already calculated, so use it to get next
  instruction
• 3 Predict Branch Taken
• 53 MIPS branches taken on average
• But havent calculated branch target address in
  MIPS
• MIPS still incurs 1 cycle branch penalty
• Other machines branch target known before outcome

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Four Branch Hazard Alternatives

• 4 Delayed Branch
• Define branch to take place AFTER a following
  instruction
• branch instruction sequential
  successor1 sequential successor2 ........ seque
  ntial successorn
• branch target if taken
• 1 slot delay allows proper decision and branch
  target address in 5 stage pipeline
• MIPS uses this

Branch delay of length n
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Scheduling Branch Delay Slots (Fig A.14)
A. From before branch
B. From branch target
C. From fall through
add 1,2,3 if 10 then
add 1,2,3 if 20 then
sub 4,5,6
delay slot
delay slot
add 1,2,3 if 10 then
sub 4,5,6
delay slot

• A is the best choice, fills delay slot reduces
  instruction count (IC)
• In B, the sub instruction may need to be copied,
  increasing IC
• In B and C, must be okay to execute sub when
  branch fails

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Delayed Branch

• Compiler effectiveness for single branch delay
  slot
• Fills about 60 of branch delay slots
• About 80 of instructions executed in branch
  delay slots useful in computation
• About 50 (60 x 80) of slots usefully filled
• Delayed Branch downside As processor go to
  deeper pipelines and multiple issue, the branch
  delay grows and need more than one delay slot
• Delayed branching has lost popularity compared to
  more expensive but more flexible dynamic
  approaches
• Growth in available transistors has made dynamic
  approaches relatively cheaper

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Evaluating Branch Alternatives

• Assume 4 unconditional branch, 6 conditional
  branch- untaken, 10 conditional branch-taken
• Scheduling Branch CPI speedup v. speedup v.
  scheme penalty unpipelined stall
• Stall pipeline 3 1.60 3.1 1.0
• Predict taken 1 1.20 4.2 1.33
• Predict not taken 1 1.14 4.4 1.40
• Delayed branch 0.5 1.10 4.5 1.45

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Problems with Pipelining

• Exception An unusual event happens to an
  instruction during its execution
• Examples divide by zero, undefined opcode
• Interrupt Hardware signal to switch the
  processor to a new instruction stream
• Example a sound card interrupts when it needs
  more audio output samples (an audio click
  happens if it is left waiting)
• Problem It must appear that the exception or
  interrupt must appear between 2 instructions (Ii
  and Ii1)
• The effect of all instructions up to and
  including Ii is totalling complete
• No effect of any instruction after Ii can take
  place
• The interrupt (exception) handler either aborts
  program or restarts at instruction Ii1

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Precise Exceptions in Static Pipelines
Key observation architected state only change in
memory and register write stages.
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Memory Hierarchy Review
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Since 1980, CPU has outpaced DRAM ...
Performance (1/latency)
CPU 60 per yr 2X in 1.5 yrs
CPU
1000
100
DRAM 9 per yr 2X in 10 yrs
10
DRAM
2000
1990
1980
Year

• How do architects address this gap?
• Put small, fast cache memories between CPU and
  DRAM.
• Create a memory hierarchy

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1977 DRAM faster than microprocessors
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Memory Hierarchy of a Modern Computer

• Take advantage of the principle of locality to
• Present as much memory as in the cheapest
  technology
• Provide access at speed offered by the fastest
  technology

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The Principle of Locality

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Two Different Types of Locality
• Temporal Locality (Locality in Time) If an item
  is referenced, it will tend to be referenced
  again soon (e.g., loops, reuse)
• Spatial Locality (Locality in Space) If an item
  is referenced, items whose addresses are close by
  tend to be referenced soon (e.g., straightline
  code, array access)
• Last 15 years, HW relied on locality for speed

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Programs with locality cache well ...
Memory Address (one dot per access)
Time
Donald J. Hatfield, Jeanette Gerald Program
Restructuring for Virtual Memory. IBM Systems
Journal 10(3) 168-192 (1971)
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Memory Hierarchy Apple iMac G5
Goal Illusion of large, fast, cheap memory
Let programs address a memory space that scales
to the disk size, at a speed that is usually as
fast as register access
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iMacs PowerPC 970 All caches on-chip
L1 (64K Instruction)
Registers
(1K)
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Memory Hierarchy Terminology

• Hit data appears in some block in the upper
  level (example Block X)
• Hit Rate the fraction of memory access found in
  the upper level
• Hit Time Time to access the upper level which
  consists of
• RAM access time Time to determine hit/miss
• Miss data needs to be retrieve from a block in
  the lower level (Block Y)
• Miss Rate 1 - (Hit Rate)
• Miss Penalty Time to replace a block in the
  upper level
• Time to deliver the block the processor
• Hit Time ltlt Miss Penalty (500 instructions on
  21264!)

52
4 Questions for Memory Hierarchy

• Q1 Where can a block be placed in the upper
  level? (Block placement)
• Q2 How is a block found if it is in the upper
  level? (Block identification)
• Q3 Which block should be replaced on a miss?
  (Block replacement)
• Q4 What happens on a write? (Write strategy)

53
Q1 Where can a block be placed in the upper
level?

• Block 12 placed in 8 block cache
• Fully associative, direct mapped, 2-way set
  associative
• S.A. Mapping Block Number Modulo Number Sets

Direct Mapped (12 mod 8) 4
2-Way Assoc (12 mod 4) 0
Full Mapped
Cache
Memory
54
A Summary on Sources of Cache Misses

• Compulsory (cold start or process migration,
  first reference) first access to a block
• Cold fact of life not a whole lot you can do
  about it
• Note If you are going to run billions of
  instruction, Compulsory Misses are insignificant
• Capacity
• Cache cannot contain all blocks access by the
  program
• Solution increase cache size
• Conflict (collision)
• Multiple memory locations mappedto the same
  cache location
• Solution 1 increase cache size
• Solution 2 increase associativity
• Coherence (Invalidation) other process (e.g.,
  I/O) updates memory

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Q2 How is a block found if it is in the upper
level?

• Index Used to Lookup Candidates in Cache
• Index identifies the set
• Tag used to identify actual copy
• If no candidates match, then declare cache miss
• Block is minimum quantum of caching
• Data select field used to select data within
  block
• Many caching applications dont have data select
  field

56
Direct Mapped Cache

• Direct Mapped 2N byte cache
• The uppermost (32 - N) bits are always the Cache
  Tag
• The lowest M bits are the Byte Select (Block Size
  2M)
• Example 1 KB Direct Mapped Cache with 32 B
  Blocks
• Index chooses potential block
• Tag checked to verify block
• Byte select chooses byte within block

Ex 0x50
57
Set Associative Cache

• N-way set associative N entries per Cache Index
• N direct mapped caches operates in parallel
• Example Two-way set associative cache
• Cache Index selects a set from the cache
• Two tags in the set are compared to input in
  parallel
• Data is selected based on the tag result

58
Fully Associative Cache

• Fully Associative Every block can hold any line
• Address does not include a cache index
• Compare Cache Tags of all Cache Entries in
  Parallel
• Example Block Size32B blocks
• We need N 27-bit comparators
• Still have byte select to choose from within
  block

59
Q3 Which block should be replaced on a miss?

• Easy for Direct Mapped
• Set Associative or Fully Associative
• LRU (Least Recently Used) Appealing, but hard to
  implement for high associativity
• Random Easy, but how well does it work?

60
Q4 What happens on a write?
Additional option -- let writes to an un-cached
address allocate a new cache line
(write-allocate).
61
Write Buffers for Write-Through Caches
Q. Why a write buffer ?
A. So CPU doesnt stall
Q. Why a buffer, why not just one register ?
A. Bursts of writes are common.
Q. Are Read After Write (RAW) hazards an issue
for write buffer?
A. Yes! Drain buffer before next read, or check
write buffers for match on reads
62
5 Basic Cache Optimizations

• Reducing Miss Rate
• Larger Block size (compulsory misses)
• Larger Cache size (capacity misses)
• Higher Associativity (conflict misses)
• Reducing Miss Penalty
• Multilevel Caches
• Reducing hit time
• Giving Reads Priority over Writes
• E.g., Read complete before earlier writes in
  write buffer

63
Virtual Memory
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What is virtual memory?

• Virtual memory gt treat memory as a cache for the
  disk
• Terminology blocks in this cache are called
  Pages
• Typical size of a page 1K 8K
• Page table maps virtual page numbers to physical
  frames
• PTE Page Table Entry

65
Three Advantages of Virtual Memory

• Translation
• Program can be given consistent view of memory,
  even though physical memory is scrambled
• Makes multithreading reasonable (now used a lot!)
• Only the most important part of program (Working
  Set) must be in physical memory.
• Contiguous structures (like stacks) use only as
  much physical memory as necessary yet still grow
  later.
• Protection
• Different threads (or processes) protected from
  each other.
• Different pages can be given special behavior
• (Read Only, Invisible to user programs, etc).
• Kernel data protected from User programs
• Very important for protection from malicious
  programs
• Sharing
• Can map same physical page to multiple
  users(Shared memory)

66
Large Address Space Support

• Single-Level Page Table Large
• 4KB pages for a 32-bit address ? 1M entries
• Each process needs own page table!
• Multi-Level Page Table
• Can allow sparseness of page table
• Portions of table can be swapped to disk

67
VM and Disk Page replacement policy
Dirty bit page written. Used bit set to 1 on
any reference
Set of all pages in Memory
Architects role support setting dirty and used
bits
68
Translation Look-Aside Buffers

• Translation Look-Aside Buffers (TLB)
• Cache on translations
• Fully Associative, Set Associative, or Direct
  Mapped
• TLBs are
• Small typically not more than 128 256 entries
• Fully Associative

hit
miss
VA
PA
TLB
Cache
Main Memory
CPU
Translation with a TLB
hit
miss
Trans- lation
data
69
What Actually Happens on a TLB Miss?

• Hardware traversed page tables
• On TLB miss, hardware in MMU looks at current
  page table to fill TLB (may walk multiple levels)
• If PTE valid, hardware fills TLB and processor
  never knows
• If PTE marked as invalid, causes Page Fault,
  after which kernel decides what to do afterwards
• Software traversed Page tables (like MIPS)
• On TLB miss, processor receives TLB fault
• Kernel traverses page table to find PTE
• If PTE valid, fills TLB and returns from fault
• If PTE marked as invalid, internally calls Page
  Fault handler
• Most chip sets provide hardware traversal
• Modern operating systems tend to have more TLB
  faults since they use translation for many things
• Examples
• shared segments
• user-level portions of an operating system

70
Example R3000 pipeline
MIPS R3000 Pipeline
Dcd/ Reg
Inst Fetch
ALU / E.A
Memory
Write Reg
TLB I-Cache RF Operation
WB
E.A. TLB D-Cache
TLB 64 entry, on-chip, fully associative,
software TLB fault handler
Virtual Address Space
ASID
V. Page Number
Offset
12
6
20
0xx User segment (caching based on PT/TLB
entry) 100 Kernel physical space, cached 101
Kernel physical space, uncached 11x Kernel
virtual space
Allows context switching among 64 user processes
without TLB flush
71
Reducing translation time further

• As described, TLB lookup is in serial with cache
  lookup
• Machines with TLBs go one step further they
  overlap TLB lookup with cache access.
• Works because offset available early

72
Overlapping TLB Cache Access

• Here is how this might work with a 4K cache
• What if cache size is increased to 8KB?
• Overlap not complete
• Need to do something else. See CS152/252
• Another option Virtual Caches
• Tags in cache are virtual addresses
• Translation only happens on cache misses

73
Problems With Overlapped TLB Access

• Overlapped access requires address bits used to
  index into cache do not change as result
  translation
• This usually limits things to small caches, large
  page sizes, or high
• n-way set associative caches if you want a large
  cache
• Example suppose everything the same except that
  the cache is increased to 8 K bytes instead of 4
  K

11
2
cache index
00
This bit is changed by VA translation, but is
needed for cache lookup
12
20
virt page
disp
Solutions go to 8K byte page sizes
go to 2 way set associative cache or SW
guarantee VA13PA13
2 way set assoc cache
1K
10
4
4
74
Summary Control and Pipelining

• Next time Read Appendix A
• Control VIA State Machines and Microprogramming
• Just overlap tasks easy if tasks are independent
• Speed Up ? Pipeline Depth if ideal CPI is 1,
  then
• Hazards limit performance on computers
• Structural need more HW resources
• Data (RAW,WAR,WAW) need forwarding, compiler
  scheduling
• Control delayed branch, prediction
• Exceptions, Interrupts add complexity
• Next time Read Appendix C, record bugs online!

75
Summary 1/3 The Cache Design Space

• Several interacting dimensions
• cache size
• block size
• associativity
• replacement policy
• write-through vs write-back
• write allocation
• The optimal choice is a compromise
• depends on access characteristics
• workload
• use (I-cache, D-cache, TLB)
• depends on technology / cost
• Simplicity often wins

Cache Size
Associativity
Block Size
Bad
Factor A
Factor B
Good
Less
More
76
Summary 2/3 Caches

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Temporal Locality Locality in Time
• Spatial Locality Locality in Space
• Three Major Categories of Cache Misses
• Compulsory Misses sad facts of life. Example
  cold start misses.
• Capacity Misses increase cache size
• Conflict Misses increase cache size and/or
  associativity. Nightmare Scenario ping pong
  effect!
• Write Policy Write Through vs. Write Back
• Today CPU time is a function of (ops, cache
  misses) vs. just f(ops) affects Compilers, Data
  structures, and Algorithms

77
Summary 3/3 TLB, Virtual Memory

• Page tables map virtual address to physical
  address
• TLBs are important for fast translation
• TLB misses are significant in processor
  performance
• funny times, as most systems cant access all of
  2nd level cache without TLB misses!
• Caches, TLBs, Virtual Memory all understood by
  examining how they deal with 4 questions 1)
  Where can block be placed?2) How is block found?
  3) What block is replaced on miss? 4) How are
  writes handled?
• Today VM allows many processes to share single
  memory without having to swap all processes to
  disk today VM protection is more important than
  memory hierarchy benefits, but computers insecure
• Prepare for debate quiz on Wednesday