A 20Gbps Serial Link for HighLoss Channels

1
A 20-Gbps Serial Link for High-Loss Channels

• Sameh Ibrahim
• Behzad Razavi

2
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Conclusions and future work

3
Motivation

• Many applications require data transmission in
  the Gb/s range.
• Manufacturers are seeking data rates in the range
  of 20 Gb/s and beyond.
• At such high speeds, many design challenges exist.

4
Frequency-Dependent Loss

• Conductor and Dielectric Loss

5
Cross-Talk
6
Reflections
7
A Practical Backplane Example
8
Measured FR4 Traces Losses
9
Equalizer Classifications

• Tx vs. Rx Equalization
• Digital vs. Analog
• Linear vs. Non-Linear

TX Eq
RX Eq
Transmission Channel
ADC
FFE
Slicer

FBE
DFE
Analog Equalizer
Sense Amplifier
Adaptation
10
Equalizers of Interest

• Linear but with multi-tone signaling
• Non-linear DFE in analog domain

11
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Current and future work

(ISSCS July 2009)
12
Multi-Tone Signaling
fc1
Transmitter
S/P
LPF
Mod
fc2
LPF
Mod
Binary Data

fcN
LPF
Mod
Channel
fc1
P/S
Demod
LPF
fc2
Demod
LPF
Binary Data
fcN
Demod
LPF
Receiver
13
Advantages of Multi-Tone Signaling

• In every subchannel, processing can be done at a
  lower rate.
• Equalization can be simple or abandoned.
• Longer symbol time improves immunity to impulse
  noise.
• Allows discrete pre-emphasis. (discussed later)
• No need for high-speed mux/demux, PLLs or CDR
  circuits.

14
Challenges

• Complexity
• Modulation type implementation.
• RF operations quadrature mixers oscillators.
• PLLs and CDR circuits.
• DACs and ADCs.
• Circuit Design
• TX RX linearity.
• Problem of harmonics.
• I/Q mismatches.
• Effect of adjacent channels.
• Tilt correction.

15
Shall we Proceed with Multi-tone?

• While the equalization task is simple in
  multi-tone signaling, new design challenges are
  introduced.
• The complexity of the system prevents its use
  whenever a binary solution is possible.
• For very high data rates or multi-band
  transmission channels, multi-tone signaling is an
  attractive choice.

16
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Current and future work

(Submitted ISSCC 2010)
17
DFE Main Equation
DFE
xrec
yeq
Slicer
xtr(n-1),xtr(n)

_
xfb
Loop Delay lt UI 50ps
xtr(n-1)
FF
A
xrec(n)hoxtr(n)h1xtr(n-1)
xfb(n)Axtr(n-1)
DFE
yeq(n)hoxtr(n)h1xtr(n-1)- Axtr(n-1)
FFE
If A h1 yeq(n)hoxtr(n)
18
Advantages and Disadvantages of DFEs
Equalized Data
ADC
FFE
Slicer
Received Data

FBE
DFE

• Best performance
• Corrects both loss and reflections
• Dont increase cross-talk
• High power (especially digital)
• Timing constraints

19
DFE Implementations

• Normal implementation

• Unrolled implementation

• Relaxes time constraints.
• Reduces the loading at the summing node.
• Increases complexity.

20
Prior Art

• Few CMOS solutions for rates near 20 Gb/s have
  been reported.

21
Direct Full-Rate DFE
R
R
R
Received Data
Equalized Data
2/R
h1
h6
h2
tc2q tsetup tFB lt UI 50ps
22
Unrolled Full-Rate DFE
R
R
R
2/R
h1
h6
h2
Received Data
Equalized Data
R
R
R
2/R
h1
h6
h2
tc2q tsetup tc2q,MUX lt UI 50ps
23
Direct Half-Rate DFE
R
R
R
tc2q tsetup tFB lt UI 50ps
Even Data
2/R
h1
h6
h2
Received Data
R
R
R
Odd Data
2/R
h1
h6
h2
24
Multiplexed Half-Rate DFE
R
R
Even Data
Received Data
2/R
h1
h6
h2
tc2q tsetup tprop,MUX tFB lt UI 50ps
Can be merged
Odd Data
Payne et al., JSSC Dec 2005
25
Unrolled Half-Rate DFE
R
R
L
L
2/R
h1
h6
h2
Even Data
R
R
R
L
L
2/R
h1
Received Data
tc2q tsetup tc2q,MUX lt UI 50ps
h6
h2
R
R
L
L
2/R
h1
h6
h2
Odd Data
R
R
R
L
L
2/R
Bulzacchelli et al., JSSC Dec 2006
h1
h6
h2
26
Multiplexed Unrolled Half-Rate DFE (1)
R
R
Even Data
Received Data
2/R
h1
h6
h2
Odd Data
27
Multiplexed Unrolled Half-Rate DFE (2)
R
R
Received Data
Even Data
2/R
h6
h2
h1
Odd Data
28
Multiplexed Unrolled Half-Rate DFE (3)
R
R
Even Data
2/R
h6
h2
h1
Received Data
R
R
L
L
2/R
Odd Data
h1
h6
h2
29
Multiplexed Unrolled Half-Rate DFE (4)
R
R
Even Data
2/R
h1
h6
h2
Received Data
R
R
L
L
2/R
h1
Odd Data
h6
h2
tc2q tsetup tc2q,MUX tprop,MUX lt UI 50ps
30
Merged MUXs Block
Q1
Ze
Q
Q1
Q0
Q
Q0
Zo
Ze
Clk
Zo
Clk
31
Multiplexed Unrolled Half-Rate DFE (5)
R
R
Even Data
2/R
h1
h6
h2
Received Data
R
R
L
L
2/R
h1
Odd Data
h6
h2
tc2q tsetup td2q,MM lt UI 50ps
32
Multiplexed Unrolled Half-Rate DFE (6)
Even Data
R
R
2/R
h1
h6
h2
Received Data
R
R
L
L
2/R
h1
h6
h2
Odd Data
td2q td2q,MM lt UI 50ps
33
Multiplexed Unrolled Half-Rate DFE (7)
Even Data
R
R
2/R
h1
Received Data
h6
h2
2/R
L
L
h1
R
R
Odd Data
34
Multiplexed Unrolled Half-Rate DFE (8)
Even Data
R
R
A
1/R
h1
Received Data
h6
h2
A
1/R
L
L
h1
R
R
Odd Data
Clk 1
Clk 2
35
Final Proposed Equalizer
Even Data
R
R
A
1/R
h1
Received Data
FFE
h6
h2
A
1/R
L
L
h1
R
R
Odd Data
Clk 1
Clk 2
36
Final Proposed 1-Tap Equalizer
37
Proposed Architecture Advantages (1)

• Half-rate clocking with loop unrolling to achieve
  better timing constraints.
• Amplifiers added in speculation paths to increase
  the swing applied to the MUX and allow faster
  current steering .
• Multiplexing the two branches reduces the number
  of summing nodes saving power and are.
• A latch rather than a flipflop can be used as the
  feedback memory element improving the speed of
  the critical path.

38
Proposed Architecture Advantages (2)

• Using stacked MUXs saves the delay of one MUX in
  the critical path.
• Inductive peaking is used to extend the bandwidth
  of all the blocks in the critical path.
• Half-rate clocking enables the use of
  higher-swing clocks and better phase accuracy.
• Half-rate clocking also enables the use of
  lower-power CDRs.

39
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Current and future work

40
Linear Equalizer
41
Linear Equalizer Simulation Results
42
DFE Circuit Realization

• CML latches and MUX with class AB biasing and
  inductive peaking.
• R1 is added to adjust the DC for direct coupling
  to the stacked MUX block.

43
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Current and future work

44
Layout
Input
Output
Clock
Core
Diff. TLs
800 µm
Serial Interface Bus
DC Pads and ESDs
1.4 mm
45
SIB

• 13 bits
• h1Coefficient 61(sign) bits
• Linear Equalizer Control 3 bits
• Clock Buffer Control 3 bits

46
Core
MR
Clock Buffer
Delay Stage
B
Delay Stage
CC
Output Buffer
CC
Summing Node Inductors
MR Matching Resistors CC Coupling
Capacitors C MUX Current Multiplexers B
Biasing
Feedback Latch
Amplifier
350 µm
Merged MUXs
Latches
C MUX
Gm
Amplifier
Feedback Latch
MR
Summing Node Inductors
Output Buffer
300 µm
B
Current Sources
47
Inductors

• Multi-layer stacked inductors to reduce area
• M3, M6 and M9 used to reduce capacitance
• Modeled by HFSS and Matlab

48
Die Photos
49
Outline

• Definition of the problem
• Architectural solutions
• Multi-Tone
• DFE
• Circuit solutions
• Layout solutions
• Measurement results
• Current and future work

50
PCB Board

• 2 layers
• No components or exposed traces in bottom layer
• Enough space for probing

3.50 inch
3 inch
51
PCB Photo
52
Wire Bonding

53
Test Setup
Centellax MS4S1M
Centellax TG2P1-A
FR4 Trace
ZRON8
Centellax UXC20P
/2
Centellax TG1B1-A
10 GHz
To Scope Trigger
Centellax MD1S4M
ZVA-183
Agilent E8257D
Agilent E8257D
10 GHz
54
Setup Photo
55
PRBS Generator Output
horizontal scale 20 ps/div vertical scale 100
mV/div

• 20-Gb/s data
• 10-ps p-p Jitter
• Clock adds another 7-ps p-p jitter

56
Channel Frequency Response

• 18-inch FR4 plus 2 cables
• 24 dB of loss at 10 GHz

57
DMUX Output
horizontal scale 20 ps/div vertical scale 50
mV/div

• 20-Gb/s input give 10-Gb/s output
• After 18-inch channel with 24 dB of loss
• Limited bandwith of the output buffer adds to the
  eye closure

58
Bathtub Curves
59
Performance Summary
60
Conclusions

• Conclusions
• A 1-Tap DFE running _at_ 20-Gb/s
• A DFE capable of equalizing 15 dB of loss with
  appropriate BER and eye opening
• Lowest figure-of-merit reported in literature
  (less than half of any FOM reported)