Testing Embedded Cores in SystemsonChip

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Testing Embedded Cores inSystems-on-Chip
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• Hans Kerkhoff,
• Liquan Fang,
• Milan Stancic,
• Thijs Krol
• CADTES - TDT

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Contents Core-Based Testing
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• SoC Applications
• Core Users Core Providers
• SoC DfT digital architecture (P1500)
• System partitioning
• Core test-wrapper
• DfT overhead
• Analogue Embedded Core Testing
• Conclusions

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Present System-on-Chip (1)
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• SoC analogue digital cores

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Present System-on-Chip (2)
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• Microsystem SoC analogue digital cores

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Core-Based Design
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• Cores are predesigned and verified but untested
  blocks
• Soft core (synthesizable RTL)
• Firm core (gate-level netlist)
• Hard core (non-modifiable layout, often called
  legacy core)
• Core is the intellectual property of vendor
  (internal details not available to user.)
• Core-vendor supplied tests must be applied to
  embedded cores.

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Example of Digital Core (e.g. VHDL)
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• High-Performance, Low-Power, System-on-Chip with
  SDRAM Digital Audio (Cirrus)

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Example of an Analogue Core
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• Dolphin Integration ADC, CODECs, PLL etc. (e.g.
  in GDSII layout format)

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PCB vs. SOC
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PCB SOC

• High reliability
• Fast interconnects
• Low cost
• Untested cores
• No internal test access
• Mixed-signal devices

• Tested parts
• In-circuit test (ICT)
• Easy test access
• Bulky
• Slow
• High assembly cost

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System Test a DfT Problem
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• Given the changing scenario in VLSI
• Mixed-signal integrated circuits
• Multi-Chip Module
• Intellectual property (IP) cores
• Single System-on-a-chip (SOC)
• Prepare the engineer for designing testable
  Systems-on-Chip

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Partitioning for Test
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• Partition according to test methodology
• Logic blocks
• Memory blocks
• Analog blocks
• Provide test access
• Boundary scan
• Analog test bus
• Provide test-wrappers for cores.

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Test Wrapper for a Core
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• Test-wrapper is the logic added around a core to
  provide test access to the embedded core.
• Test-wrapper provides
• For each core input terminal
• A normal mode Core terminal driven by host
  chip
• An external test mode Wrapper element observes
  core input terminal for interconnect test
• An internal test mode Wrapper element controls
  state of core input terminal for testing the
  logic inside core
• For each core output terminal
• A normal mode Host chip driven by core
  terminal
• An external test mode Host chip is driven by
  wrapper element for interconnect test
• An internal test mode Wrapper element observes
  core outputs for core test

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A Test-Wrapper
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Wrapper test controller
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Additional DfT Components
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• Test source Provides test vectors via on-chip
  LFSR, counter, ROM, or off-chip ATE.
• Test sink Provides output verification using
  on-chip signature analyzer, or off-chip ATE.
• Test access mechanism (TAM) User-defined test
  data communication structure carries test
  signals from source to module, and module to
  sink tests module interconnects via
  test-wrappers TAM may contain bus, boundary-scan
  and analog test bus components.
• Test controller Boundary-scan test access port
  (TAP) receives control signals from outside
  serially loads test instructions in test-wrappers.

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Goals of IEEE P1500
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• Core test interface between embedded core and
  system chip
• Test reuse for embedded cores
• Testability guarantee for system interconnect
  and logic
• Improve efficiency of test between core users
  and core providers

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Set-up of P1500 Architecture
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Core including Wrapper Cells
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Wrapper Registers for P1500
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P1500 Wrapper Input Cell
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Output P1500 Wrapper Cell
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Embedded Analog Core Testing
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Example Embedded Core Filter
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• Embedded core

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The Embedded Core Filter
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• Block scheme
• Transistor scheme

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Local Test Generation (filter)
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• Actual
• Test signal

Expected Simulated responses
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Analog DfT Wrappers
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AMP
FIL
VIC

• Mixed-Signal Systems-on-Chip Wrappers

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Analog Input Output Wrappers
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Analogue output wrappers

• Analogue input wrappers

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Backtracing of Test Signals
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• Fast backtracing

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Real Testing Results
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• Measurements from
• IntegraTest Verification
• Test System using Labview

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Conclusions
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• Systems-on-Chip are rapidly gaining importance

• Many core providers deliver digital as well as
  analogue cores (VHDL, netlists, layouts)

• VSIA is one of the emerging standards for design
  exchange of cores (digital analogue)

• P1500 is on its way to become a test standard
  for digital

• Analogue test standard still in its infancy.
  IEEE 1149.4 will probably serve as basis