Talk

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DEPFET Technology for future colliders
Carlos Mariñas IFIC-Valencia (Spain)
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• DEPFET (DEpleted P-channel Field Effect
  Transistor) Technology invented by J. Kemmer
  G. Lutz, 1987
• J. Kemmer and G. Lutz ''New semiconductor
  detector concepts'', Nucl. Instr. Meth. A 253
  (1987) 365-377

• Several different applications for Astrophysics
  and Particle Physics
• XEUS Future european X-ray observatory to
  investigate the Early Evolution Stages of the
  Universe (early black holes, evolution of
  galaxies)
• BepiColombo ESA project to Mercury to
  investigate the origin and evolution of the
  planet
• X-FEL
• ILC
• BELLE-II ? Technology chosen for the new Vertex
  Detector

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Why this technology?

• Vertexing in future colliders requires excellent
  vertex reconstruction and efficient heavy quark
  flavour tagging
• See Prof. Ch. Damerells talk

• This requirements impose unprecedented
  constraints on the detector
• High granularity to cope with the high density
  of tracks in the jets and the background
• High spatial resolution per layer lt4mm (pixel
  size of 25x25mm2)
• Fast read-out
• Low material budget lt0.1X0/layer (100mm of
  Si)
• Low power consumption

• DEPFET
• Measurements made on realistic DEPFET prototypes
  have demonstrated that the concept is one of the
  principal candidates to meet these challenging
  requirements

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The DEPFET principle

• Each pixel is a p-channel FET on a completely
  depleted bulk (sideward depletion). Charge is
  collected by drift
• A deep n-implant creates a potential minimum for
  electrons under the gate (internal gate)

• Signal electrons accumulate in the internal gate
  and modulate the transistor current (gq500pA/e-)
• Accumulated charge can be removed by a clear
  contact

• Small pixel size 25µm
• r/o per row 50ns (20MHz) (drain)?Fully depleted
  bulk
• Noise100e-?Small capacitance and first in-pixel
  amplification
• Thin Detectors50µm

• Internal amplification
• Low power consumption Readout on demand
  (Sensitive all the time, even in OFF state)

GOAL
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DEPFET-Principle of Operation
Potential distribution
internal Gate
1µm
Backcontact
Drain
50 µm
Source
TeSCA-Simulation
FET-Transistor integrated in every pixel (first
amplification) Electrons are collected in
internal gate and modulate the
transistor-current Signal charge removed via
clear contact
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DEPFET-Principle of Operation
Potential distribution
internal Gate
1µm
Backcontact
Drain
50 µm
Source
TeSCA-Simulation
FET-Transistor integrated in every pixel (first
amplification) Electrons are collected in
internal gate and modulate the
transistor-current Signal charge removed via
clear contact
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ILC prototype system

• Hybrid Board
• DEPFET 64x256 matrix
• Readout chip (CURO)
• Steering chips (Switchers)

• Protection Board
• Regulators

• Readout Board
• 16 bit ADCs?Digitization
• XILINX FPGA?Chip config. and synchronization
  during DAQ
• 128 kB RAM?Data storage
• USB 2.0 board?PC comm.

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Hybrid board
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Operation mode Row wise readout

• Row wise r/o (Rolling Shutter)
• Select row with external gate, read current,
  clear DEPFET, read current again ? The difference
  is the signal
• Low power consumption Only one row active at a
  time Readout on demand (Sensitive all the time,
  even in OFF state)
• Two different auxiliary chips needed (Switchers)
• Limited frame rate

Drain
Enable row Read current (Isig Iped) Clear
Read current (Iped), Subtract Move to next row
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DEPFET Concept for a half ILC module

• 10 and 25 cm long ladders read out at the ends
• 24 micron pixel
• design goal 0.1 X0 per layer in the sensitive
  region

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Thinning mechanical samples
6 wafer with diodes and large mechanical samples
Thinned area 10cm x 1.2 cm (ILC vertex detector
dummy)
Possibility to structure handling frame (reduce
material, keep stiffness)
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DEPFET achievements Test Beam Setup
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• Telescope
• 5 DEPFET planes
• 32x24µm2
• CCG
• 450 µm thick

• DUT
• 1 DEPFET modules
• Various pixel sizes
• 450 µm thick

• Scintillators
• 1 Big Beam finder
• 1 Finger Beam allignment
• Triggering

Trigger Synchronization via TLU (Trigger Logic
Unit)
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Test Beam Setup

• General view
• 6 Modules at once
• 1 rotating module

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My work

• Calibration/optimization of different
  generations of matrices
• PXD4-Clocked Cleargate. 128x64 pixels
• PXD5-Common Cleargate. 128x64 pixels
• PXD5-Capacitative Coupled Cleargate. 256x64
  pixels

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• Test Beam
• Data analysis (SNR, Residuals, Charge collection
  uniformity)

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• Mechanical/Thermal measurements and simulation
  (Finite Element An.)
• Natural frequencies, self weigth bowing,
  deformations
• Conduction, convection, thermal stress
• Power cycling
• Thermal characterization of different materials
  for cooling (Al, Cu, TPG)

Natural convection
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Thank you very much!
Belle-II, SuperB, ILC, CLIC
The LHC is not the end but just the beginning!
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