TIMING%20%20AND%20%20JITTER

1
Physics AstronomyHEP Electronics
TIMING AND JITTER
ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004
Martin PostraneckyJohn Lane, Matthew Warren
2
TIMING

• The BC clock is output to all BOC/ROD slots as
  differential PECL. Point-to-point balanced tracks
  of identical length on the backplane are used for
  all slots, providing a synchronised clock for all
  BOCs RODs
• The 8x commands TTC(n) are all clocked out onto
  the backplane simultaneously
• This TTCCLKB is delayed by an adjustable delay
  ( 6 bits of 0.5nsec ), pre-set by a ROD SETUP
  DIL switch. This allows for adjustments of the
  Setup and Hold times of the TTC(n) commands at
  the RODs to be made

3
Output Signals Timing
4
Timing of TTC Signals
5
TIM3 Clock Flow
BCCLKLED
CLOCK40
TTCrm/rq
PECL Drivers
U56
U57
CLOCK40DES1
BCCLK1B
TTCCLK1B
9x CLOCK40
U42
MCLK1
PCLKB
TTCCLK2L
U52
TTCCLK2B
FPGA2
ENSACLK
8x CLOCK40
FPGA2
CLOCK40DES2
BCCLK1B
U58 CLK MUX 2
U42
NIMEXTCLK
ROD Setup
CLKINB2
EXTCLKLED
SW8
U46 DL2
ECLEXTCLK
U36
EXTCLKB
U33
EXTCLK
ECLEXTCLK2
U48 DL1
U51
U45
CLKIN1
SACLKB
CLKINB1
DL1OUT
DL2OUT
ENINTCLK
SACLKLED
CLKIN2
U42
FPGA2
U38 CLK MUX 1
NIMCLKOUT
CT(50)
U44
FPGA2
ECLCLKOUT1
INT_CLK
80Mhz Osc.
ECLCLKOUT2
U39
DL2OUTB
CLK0
TTCout(0-7)
TTC(7-0)A
CLK00
U44
TTC(7-0)B
U44
TIM Setup
CLKINB4
U47 DL4
SW7
Trigger Window
WD(50)
FPGA2
TIMCLK1L
FPGA1
WS(50)
DL4OUT
FPGA2
TIMCLK2L
SW10
U50
FPGA2
SW9
U69 DL
TIMCLK3L
Size
U62 DL
U61 DL
U63 DL
TRIGCLK
DL4OUTB
MRMW/MP v2.0 11-05-04
Setup
Delay
Size Comp.
6
TIMING ON BACKPLANE
Clock on Test Board in Slot 14 Trigger on Test
Board in Slot 14 5.0nS/div SetUp Time 12nS Hold
Time 12nS
7
TIMING ON BACKPLANE
Clock on Test Board in Slot 21 Trigger on Test
Board in Slot 21 5.0nS/div Setup Time 10nS Hold
Time 14nS
8
JITTER ON BACKPLANE
SA CLOCK on TEST BOARD in Slot 19 SA CLOCK on
TEST BOARD in Slot 14 500ps/div Delay
10uS Max.Jitter 600pS p-p
9
JITTER ON TIM
Stand-Alone PCLKB output from TIM-3 Trigger not
running 200nS/div Delay 10uS Jitter 350pS
10
JITTER ON TIM
Stand-Alone PCLKB output from TIM-3 All TTC(n)
running 200nS/div Delay 10uS Jitter 300pS