David Miller and Jim Harris

1
Hybrid Optical Interconnects to Silicon CMOS

• David Miller and Jim Harris
• http//ee.stanford.edu/dabm
• Ginzton Laboratory and Solid State and Photonics
  Laboratory
• Stanford University

2
Personnel

• Students
• Diwakar Agarwal, Rafael Aldaz, Gordon Keeler,
  Bianca Nelson
• Senior Scientists
• Petar Atanackovic, Glenn Solomon
• Collaborators
• Prof. Mark Horowitz (Stanford), Azita
  Emami-Neyestanak
• Prof. Hugo Thienpont (VUB, Brussels), Christof
  Debaes
• Funding
• Interconnect Focus Center, DARPA Optocenters
  Program (New Mexico team)

3
Goals

• Construction and testing of complete chip-to-chip
  and on-chip optical interconnects
• crucial to attempt complete system to identify
  real compatibilities and real problems and
  benefits
• this is, however, difficult!!
• Understand key limiting factors and problems with
  these interconnects
• Understanding latency in optical interconnects
• Explore device and technology solutions to
  optical interconnect problems and performance

4
Summary

• Integration technology
• Fabricated chips
• Successful
• complete fabrication of several different chips,
• bonding and optimization of optoelectronic
  devices, and
• preliminary testing of logic and optical link
  circuits
• Latency analyzed for various circuits
• Latency tests of circuits
• Optical in electrical out
• Optical in optical out

5
Flip-Chip Bonding of Devices
Silicon CMOS chip with gold bonding pads

• Advantages of integration by flip-chip bonding
• allows the use of mature CMOS processing steps
  for circuit design
• almost any optoelectronic device can be
  integrated
• good yields have been demonstrated
• reduces the diode capacitance seen by the circuit
• reduces noise capacitively coupled through wires
  connecting diodes and circuits

GaAs optoelectronic chip with indium flip-chip
bumps
6
Optoelectronic Devices Bonded to CMOS Chips

• Quantum well modulator/detector diodes,
  fabricated at Stanford, successfully
  solder-bonded at Stanford to several different
  functional CMOS chips

7
Integration technology

• In-house flip-chip bonding process
• Several different functioning chips successfully
  bonded with good yield and uniformity
• WDM chip (0.5 micron), OPTLAT chip (0.25 micron),
  Clocked receiver chip (collaboration with Mark
  Horowitz)
• Procedure developed for tuning Fabry-Perot
  resonance of reflective modulators after bonding
• Device capacitance measured to be in good
  agreement with calculations
• 260 fF for 40 x 40 micron devices, measured
  directly and by ring oscillator frequency
• Work on improved output modulator device concept
  under way

8
Short Pulse WDM Chip-Chip Interconnect
9
WDM Interconnect

• Receiver arrays now working in second generation
  chip
• On-chip bit error rate test circuitry working
• Link testing now under way using bit error rate
  tester and parallel channels
• Chip also used for preliminary latency testing of
  optical receiver/transmitter circuits

10
2nd Generation WDM Results

• Demonstration of logic-level to logic-level WDM
  optical interconnection at 80 Mb/s (limited by
  laser repetition rate)

11
Latency in optical interconnects

• Latency is a key parameter for any short distance
  interconnect
• OPTLAT chip contains various test circuits for
  optical interconnect latency
• Tested latency in optical interconnects by direct
  measurement
• Compared with modeling
• Measured benefits of use of short optical pulses
  for interconnect latency

12
OPTLAT chip for latency testing

• Chip with various circuits to test latency of
  optical interconnects
• 0.24?m Process(?0.2 ?m)
• Default Supply2.5V
• FO4 Delay96pS
• size 2118 ?m x 2118 ?m
• 68 pads
• Now fabricated, with optoelectronic devices
  fabricated and bonded at Stanford

13
OPTLAT Chip Experiments

• Characterized silicon detectors built into OPTLAT
  Chip
• silicon detectors in conventional CMOS, though
  problematic for signal detectors because of long
  tails, may be useful for clock injection
• characterized response of silicon detectors using
• short optical pulses and
• on-chip electrical sampler circuits
• demonstrated lt100 ps fast rise component in
  signal
• potentially useful for clock injection
• Measured latency of receiver/transmitter pairs
  with bonded III-V devices
• Future planned experiments include ring
  oscillator with optical links, testing of on-chip
  interconnects with optical bridges, and
  receiver-less links for low latency and high
  noise immunity

14
On-chip Silicon Detector Rise-Times

• Measured response shows 100ps initial rise/fall
  time of detected signal (probably still limited
  by sampler bandwidth)
• May be usable for very precise clock injection

15
Latency Reduction with Short Optical Pulses

• All the energy is concentrated in a short period
• In integrating receiver with NRZ, latency is
  about half a bit period
• In transimpedance receiver, short pulses charge
  the internal nodes faster, reducing the latency

16
Simulated Latency Comparison Transimpedance
Receivers

• Comparison of simulated latency for a receiver
  driven by short pulses and one driven by NRZ
  (conventional non-return-to-zero) signal
• short pulse interconnects substantially reduce
  latency

Latency (ps)
Energy/bit (fJ)
17
Latency Measurement

• Latency results for receiver/transmitter pair in
  0.25 micron technology using transimpedance
  receivers
• Measured using optical pump-probe technique
• Measured latency, including vs. supply voltage,
  in good agreement with simulations

delay 536 ps
18
Experimental Latency Comparison Transimpedance
Receivers

• Comparison of experimental and simulated latency
  for short pulse vs. NRZ data
• Experiments confirm reduction of latency using
  short pulses

19
Receiver Sensitivity Enhancement using Short
Optical Pulses

• Complete chip-to-chip short pulse link
  demonstrated using a high-repetition-rate
  modelocked diode laser
• 3dB sensitivity enhancement in integrating
  receivers using short pulses

20
Other specific circuit work

• Successful testing of component parts of various
  optical chip-chip and on-chip interconnect
  systems
• Successful operation of receiver circuits in
  agreement with simulations
• 500 MHz operation of clocked sense amplifier
  integrating receiver in 0.5 micron technology
• 2 Gb/s operation of clocked optical CMOS
  receiver with bonded quantum well diodes
  (collaboration with Mark Horowitz) in 0.25 micron
  technology
• Preliminary testing of sense amplifier and
  transimpedance receivers to gt 500 Mb/s for
  latency tests in 0.25 micron technology
• Testing of sensitivity of receivers to circuit
  noise
• Electrical testing of on-chip pseudo-random bit
  sequence generator (up to 700 Mb/s, limited by
  silicon flip-flop logic speed) and bit-error-rate
  tester circuits in 0.5 micron technology

21
Silicon on insulator chip

• Silicon on insulator chip designed for testing of
  
• high performance receiver circuits
• fast silicon photodetectors
• benefits of ultra low capacitance (e.g., 10 fF)
  detectors

22
Conclusions

• Several different silicon chips now successfully
  fabricated, with optoelectronic devices
  successfully bonded
• Several working optical links and receivers
• Work continuing on
• system demonstrations
• improved devices and circuits
• benefits of short pulses
• clock injection
• Detailed analysis and results on latency in
  optical receivers and transmitters
• physical latency of optical links is not
  fundamentally long, and is comparable to or
  better than typical electrical links
• latency, especially with short optical pulses,
  may be good enough for use on chip