The future of rad-tol electronics for HEP

1
The future of rad-tolelectronics for HEP

• Giovanni Anelli Alessandro Marchioro
• CERN
• Experimental Physics Division
• Microelectronics Group

2
What comes after

• SLHC
• Luminosity 1035 fb-1
• Beam cms energy same
• Radiation levels (5 years) 200 Mrad _at_ 7 cm, 40
  Mrad _at_ 20 cm
• Compensate for higher intensity through higher
  segmentation
• Cost lower than current !
• Power/channel must decrease

3
What if SLHC ?

• If 5x luminosity 1 tracker would require
• 2 x speed
• 2x segmentation ? 20 M channels
• 25 higher occupancy
• Assuming that (magically) FE power/ch remains the
  same, the CMS tracker would require
• Ptot 60 kW
• Pcables 150 kW
• CablesF double, cooling pipes double

1 This is purely hypothetical, actual numbers
may change
4
Outline

• Where is technology going (anyway)
• Problems with following technology
• What makes CMOS rad-tolerant
• Is technology all what we need ?

5
Saving power Technology
LHC Start
SLHC Start
1997 1999 2001 2003 2006 2009 2012
Overall Characteristics Transistor
density (2) 3.7 M/mm2 6.2 M/mm2 10 M/mm2 18
M/mm2 39 M/mm2 84 M/mm2 180 M/mm2 Chip size
(3) 300 mm2 340 mm2 385 mm2 430 mm2 520 mm2
620 mm2 750 mm2 Local clock frequency (4)
750 MHz 1.25 GHz 1.5 GHz 2.1 GHz 3.5 GHz 6
GHz 10 GHz Power supply voltage (5) 1.8-2.5V
1.5-1.8V 1.2-1.5V 1.2-1.5V .9-1.2V .6-.9V
.5-.6V Maximum power (6) 70 W 90 W 110 W
130 W 160 W 170 W 175 W Technology
Requirements µP channel length (1) .20
µm .14 µm .12 µm .10 µm 70 nm 50 nm 35 nm
DRAM ½ pitch (1) .25 µm .18 µm .15 µm .13
µm .10 µm 70 nm 50 nm Tox Equivalent (7)
4-5 nm 3-4 nm 2-3 nm 2-3 nm 1.5-2 nm lt1.5
nm lt1.0 nm Gate Delay Metric CV/I (7) 16-17
ps 12-13 ps 10-12 ps 9-10 ps 7 ps 4-5 ps
3-4 ps Solutions Exist Solutions Being
Pursued No Known Solution
6
Moores law
http//www.intel.com/
An example Intels Microprocessors
7
When will it stop ?
Tox (A)
Carver Meads Law tox 210 L 0.77 from C.
Mead, Scaling of MOS Technology to Submicron
Feature Sizes, Journal of VLSI Signal
Processing, July 1994
8
Why is CMOS so widespread?

• IC market is driven by digital circuits
  (memories, microprocessors, )
• Bipolar logic and NMOS - only logic too high
  power consumption per gate
• Many improvements in the manufacturing technology
  made CMOS technologies a reality
• Modern CMOS technologies offer excellent
  performance high speed, low power consumption,
  VLSI, low cost, high yield

CMOS technology occupies a dominant position of
the IC market
9
Following technologies

• We have no choice other than follow industry,
  but
• Industry may move to SOI
• Substrates and isolation will change
• Gate oxides are going down to atomic levels
• Our volume is dangerously small
• CMOS is engineered primarily for digital
  applications
• VDD is going down (analog harder and harder)
• Most of our circuits are mixed signal and
  modeling for analog is poorer
• ¼ micron is well adapted to our designs, was it
  just good luck ?

10
Constant field scaling
11
Constant field scaling problem
Subthreshold slope and width of the moderate
inversion region do not scale!!!
log ID
nA
pA
0 V
VGS
12
Challenges for the future(See the talk by Y.
Taur 9/Jul/01)

• Lithography
• Leakage currents
• Gate oxide (materials, tunneling, reliability)
• Wiring and interconnections (materials)
• Many metal layers (up to 10)
• Design complexity (CAD tools)
• Cost of fabs

13
Power Not only our problem
Source P. Gelsinger, Intel Corp. Presentation at
the ISSCC 2001
14
Problem device leakage
Source D. Frank et al., Proceedings of the
IEEE, 3/2001
0.1 mm technology Will have a leakage Current of
100A/cm2
Source P. Gelsinger, Intel Corp. Presentation
at the ISSCC 2001
15
Ideal Analog Technology

• Several considerations suggest that the 0.35 mm
  or perhaps the 0.25 mm BiCMOS technology will
  be adequate
• B. Gilbert, Analog at Milepost 2000,
  
• Proc. of the IEEE, 3/2001
• Reasons
• Cost of high performance technologies
• No need for extreme scaling in analog
• Limited supply voltage
• Limited topologies
• Limited signal swing (dyn-range)

16
Scaling impact on analog circuits
With tox reduced and for the same device
dimensions

• Threshold voltage matching improves
• 1/f noise decreases
• Transconductance increases (same current)

17
Scaling impact on analog circuits

• New noise mechanisms
• Modeling difficulties
• Lack of devices for analog design
• Reduced signal swing (new architectures needed)
• Substrate noise in mixed-signal circuits
• Velocity saturation. Critical field 3 V/?m for
  electrons, 10 V/?m for holes

18
What makes CMOS rad-tol

• Radiation tolerant design
• The Enclosed Layout Transistor (ELT)
• Guard rings
• SEE tests

19
Transistor level leakage (NMOS)
20
Single Event Upset (SEU)
21
?VT and tox scaling
22
Radiation tolerant layout approach
23
Enclosed Layout Transistor (ELT)
ELTs solve the leakage problem in the NMOS
transistors At the circuit level, guard rings
are necessary
24
Effectiveness of ELTs
0.7 ?m technology - tox 17 nm
25
Effectiveness of ELTs
0.5 ?m technology - tox 10 nm
26
ELT deep submicron
0.25 mm technology - tox 5 nm
27
Total dose results up to 30 Mrad
Threshold voltage
Leakage current
Annealing
Annealing
Output conductance
Mobility degradation lt 6 NMOS lt 2 PMOS
NMOS L0.28
PMOS L0.28
NMOS L2
0.25 ?m technology
PMOS L2
28
Radiation tolerant layout approach
p guard ring
n guard ring
OUT
IN
VSS
VDD
metal
polysilicon
n diffusion
p diffusion
29
Single Event Upset tests
F. Faccio et al., Single Event Effects in Static
and Dynamic Registers in a 0.25 ?m CMOS
Technology, IEEE Transactions on Nuclear
Science, vol. 46, no. 6, Dec. 1999 , pp.
1434-1439.
30
Comparison with the general trend
31
What if deeper submicron ?

• SEU will be an even bigger problem
• Possible remedies
• Triple redundant logic
• Error correcting logic
• Self-checking FSM
• Consequences
• Higher power consumption

32
Density and speed
A B 0.6 ?m standard
C D 0.25 ?m rad-tol
Inverter with F.O. 1
33
Is technology enough ?

• The next issue is power consumption, and not just
  technology
• Need work at all levels
• Technology
• Circuits
• Architecture
• Algorithms

34
Power in CMS Tracker worst case 1)

• Total channels 75,500 FE chips x 128 10M
• Power/FE 2.3 mW/channel
• Pwr/ch data TX 0.6 mW/channel
• Supply 2.5 V and 1.25 V, Ptot 30 kW
• Total FE currents IDD125 7.5 kA, IDD250
  6.5 kA
• Remote supplies ? of service cables 1,800
• Power in the cables gt 75 kW
• Cross section of power cables and cooling pipes
  directly proportional to power dissipated !

1) Worst case is computed after 10 years of
irradiation
35
Material budget in CMS Tracker
36
Saving power in VLSI circuits

• Technology scaling
• Advanced technology, packaging, scaling
• Circuit and logic topologies
• Device sizing, Logic optimization (digital),
  Power down (sleep) mode
• Architecture (analog and digital)
• Signal features (e.g. correlation), Data
  representation, Concurrency, Partitioning
• Algorithms
• Regularity, Data Representation, Complexity

37
Designing chips

• Designing chips is very difficult
• Need clear objectives
• Errors are unforgiving
• Need complex tools
• Analog designers suffer of frequent technology
  changes
• Most HEP designs are mixed A-D (even worse !)
• Need large teams and large investments
• Need time and continuous training
• Need good engineers
• Need long term commitments
• Need complex infrastructure
• Need stable partnership with foundry
• Need good and supportive management
• The last 10 takes 90 of the time

38
Time investment Custom components
Manyears Iterations
APV25 gt10 many
PLL 4 3
MUX 1 3
CCU 5 2
DCU 3 3
LD 2 3
TTCrx 5 4
Lib Dev 2 ?
APV25
Detector Control Unit (DCU)
39
Example Library development

• First approach
• Well, lets layout some gates and we are done

• Reality
• Complete set of tools to fit library into CAD
  system
• Simulation (timing) models of each gate under all
  load and operating conditions
• Models for synthesis
• Wire load models (small, medium, large designs)
• Extraction models
• Iterate with each new release of tools

40
Reliability how much risk can you take ?

• Did you simulate process corners ?
• Device/technology modeling
• Did you look at electro-migration ?
• Did you optimize your design for yield ?
• ESD are you following the rules ?
• How safe is your protection circuit ?
• How well was the chip characterized ?
• IC Tester or application specific test-bench ?
• If the chip works ok on the ASTB, how much margin
  do you really have ?
• Will your users follow your application
  recommendation ?

41
Miscellaneous issues

• Industry is moving to 12 wafers
• The total need for microelectronics for LHC in
  1998 was corresponding to small of the annual
  production of typical producer in industry
• We need a large number of prototyping cycles
• Do we have the money ?
• Will they care about us ?
• Do we have the structure necessary to design
  large chips ?

42
Conclusions

• Our community has no choice other than follow the
  trend in industry
• But we are not normal users, need access to
  more info that foundries typically give
• To adapt a technology for rad-tol requires many
  man-years of work Need to work with a minimum
  of technologies
• Dont look at the cheapest (short-term) because
  what really matters is service and support
• Our cost is dominated by design cost and not
  production

43
Web

• Slides summarizing some of the talks organized
  for the microelectronics day organized by Erik
  Heijne athttp//cern.ch/Snowmass2001