Title: Part I' Sequential Circuits
1Part I. Sequential Circuits
2Flip-Flops Latches
3Latches Flip-Flops
- Sequential circuits remember the past, i.e.,
the output depends not only on the present input
but also on the past sequence of inputs. - Latches and Flip-flops are commonly used storage
element (memory devices) in sequential circuits. - A memory element that has no clock input is often
called a latch. - A flip-flop has a clock input, and the flip-flops
can only change state in response to a clock
pulse. - A basic rule of latch operation outputs are
complements to each other
4Timing Diagrams
- There is a time delay between the inputs and the
corresponding outputs - called propagation delay - In sequential circuit analysis, short delays may
be important - use timing diagrams
x
x
x
x
?1
?2
In the range of nanoseconds (10-9 sec)
5 SR Latch (Set Reset)
Q
Q
S
R
6SR Latch Operation
Represented by a state (Q Q)
Assuming start from hereS0R0
01
Stable state S0, R0, assume Q0, then Q1
This circuit is said to have memory because its
output depends not only on the present inputs,
but also on the past sequence of inputs.
7SR Flip-Flop Operation Table
Assuming start from hereS0R0
Q(t?)
S(t)
R(t)
Q(t)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 not allowed
1 1 1 not allowed
Restriction S and R cannot be 1 simultaneously
because otherwise both Q and Q will be 0
8SR Latchs next-state equation
Use K-Map obtain Q(t?) S(t)R(t)Q(t) or
denoted as QSRQ (SR0)
Meaning S and R cannot both be 1 at the same time
(The restriction)
9Gated D (Delay) Latch
?
?
D
?
Q
C
Q
?
?
?
Q
C
D
No change
0
X
1
0
Q0 Reset
1
1
Q1 Set
10D Flip Flop
Q D
Q
Q
clock
CK
D
The flip-flop changes state on the falling edge
of the clock pulse
D
Clock
Q
11T Flip-Flop
Q TQTQT? Q
Q
Q
CK
T
clock
clock
T
Q
The flip-flop changes state on the falling edge
of the clock pulse
12The J-K Flip-Flop
Q
Q
- If J1, the flip flop is set to Q1
- If K1, the flip flop is set to Q0
- If both J and K are 1, the flip flop behaves like
a T flip flop
Q
Q
S0R0
R
S
01
J
K
Q QK QJ
13The clocked J-K Flip Flop
Q
Q
Q
CK
K
J
CK
Falling edge-triggered
J
K
14JK Flip-Flops with Clear and Preset Inputs
- Clear input 0 will reset the flip-flop to Q0
- Preset input 0 will set the flip-flop to Q1
Q
Q
Q
Q
Q
Q
Clear
Preset
CK
CK
CK
D
Clear
D
Clear
K
J
Falling edge triggered
Rising edge triggered
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15Homework 1
- Review ECE204 Flip Flop Latches Part
- 11.7, 11.9, 11.11, 11.13(a), 11.17, 11.19
- Due?
16Registers Counters
A register consists of a group of flip-flops with
a common clock input. Registers are commonly
used to store and shift binary data. A counter
is usually constructed from two or more
flip-flops which change states in aprescribed
sequence when input pulses are received.
17Application of Flip Flops - Registers
Data Out
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
CLR
CLR
CLR
CLR
D1
CK
D2
CK
D3
CK
D4
CK
clock
clear
1
1
1
0
Data In
188-bit Register with Tri-State Output
Enable
clock
D1
D2
D7
D8
19Data Transfer using a Tri-State Bus
1
8
8
Bus
8
8
8
8
Decoder
20Synchronous Binary Counter
Counter outputs
A
B
C
A
B
C
TB
TA
TC
Pulse
21Counter outputs
A
B
C
A
B
C
TB
TA
TC
Pulse
Pulse
TC
C
TB
B
TA
A
000
001
010
011
100
101
110
111
22Design of the Binary Counter (1)
Next State
Inputs
Present State
A
B
C
A
B
C
TA
TB
TC
0 0 0
0 0 1
0 0 1
0 0 1
0 1 0
0 1 1
0 1 0
0 1 1
0 0 1
0 1 1
1 0 0
1 1 1
1 0 0
1 0 1
0 0 1
1 0 1
1 1 0
0 1 1
1 1 0
1 1 1
0 0 1
1 1 1
0 0 0
1 1 1
23Design of the Binary Counter (2)
When design using T flip flop, whenever a change
of state is required, the T input must be 1
Q
Q
T
0 0 0 1 1 0 1 1
T Q Q
0 1 1 0
C changes state every time a pulse is received.
The pulse source must be connected directly to
TC.
TC P
TA and TB are derived from the corresponding
K-Map
TA BCP
TB CP
24A Counter Design using T FF (1)
Develop the state table
000
Present State
Next State
A
B
C
A
B
C
100
011
0 0 0
1 0 0
0 0 1
- - -
0 1 0
0 1 1
111
010
0 1 1
0 0 0
1 0 0
1 1 1
1 0 1
- - -
1 1 0
- - -
1 1 1
0 1 0
25A Counter Design using T FF (2)
Derive the next state map from the previous state
table
A
0
1
0
1
0
1
A
B
C
A
B
C
BC
BC
BC
00
00
00
1 0 0
1
1
0
1
0
1
0 0 0
- - -
01
01
01
0 0 1
x
x
x
x
x
x
0 1 1
0 1 0
11
11
11
0
0
1
0
0
0
0 0 0
0 1 1
10
10
10
0
x
1
x
1
x
1 1 1
1 0 0
- - -
A
B
C
1 0 1
- - -
1 1 0
0 1 0
1 1 1
26A Counter Design using T FF (3)
Derive the T inputs using next state map The
basis Whenever there is a state change, the
corresponding T is 1
A
A
A
0
1
0
1
0
1
BC
BC
BC
00
00
00
1
1
0
1
0
1
01
01
01
x
x
x
x
x
x
11
11
11
0
0
1
0
0
0
A
A
A
0
1
0
1
0
1
10
10
10
0
x
1
x
1
x
BC
BC
BC
00
00
00
1
0
0
1
0
1
A
B
C
01
01
01
x
x
x
x
x
x
11
11
11
1
0
0
1
1
1
10
10
10
0
x
0
x
1
x
TA
TB
TC
27A Counter Design using T FF (4)
TA ABAB (AB)(AB)
Pulse
TB ACAB (AB)(AC)
TC AB
- The initial states of the flip-flops may be
unpredictable. - Make sure all the dont care states will lead to
the main sequence
28DIY
- Design a counter of your own using T Flip Flop
29 ROM
decoder
Memory Array 2n x m
- ROM (Read Only Memory) An array of semiconductor
devices that are interconnected to store an array
of binary data. - A ROM with n input lines and m output lines
contains an array of 2n words, where each word is
m bits long.
30Hexadecimal to 7-bit ASCII Code Converter
- Derive the truth table
- Notice the relationship between A4, A5, and A6
- Design such a converter using a ROM with 16 words
by 5 bits - Draw the internal design of the ROM
31EPROM
32State Machines
33Mealy Moore Machines
- Moore machine
- the output depends only on the present state
- Mealy machine
- the output depends on both the present state and
also on the inputs
34Sequential Parity Checker
- Parity Bit
- Purpose error detection
- How does it work? Parity1 if the sum of the data
is odd, otherwise parity0 (or vice versa). - Examples 0001000 1 ? 0011000 1
- Can parity bit detect all kinds of errors?
Error occurred
35Design of a Parity Checker
- Serial Data Input, one bit at a time
- Z1, if the total number of 1 inputs is odd
Otherwise Z0
Parity Checker
Data (X)
Z
Clock (P)
1
1
1
1
1
1
0
0
0
0
0
X
P
ZQ
36State Graph for Parity Checker
X1
S0Z0
S1Z1
X0
X0
X1
Only two states Use Q to represent Z
Q
X
Q
Q X?Q
0 0
0 1 1 0
0 1
Which flip flop satisfy this?
1 0
1 1
37Characteristic Equations
- S R Flip Flop
- Q S RQ (SR0)
- T Flip Flop
- Q T ? Q TQTQ
- J K Flip Flop
- Q JQKQ
- D Flip Flop
- Q D
38Parity Checker Flip Flop Design
Parity Checker
Data (X)
Z
P
Z
Q
Q
CK
T
P
Data (X)
39Design a Party Checker using EPROM
- Inputs
- Outputs
- Assume initial condition
- How do you realize the logic?
This is the output
40Example
EPROM
?
decoder
X
Z
41Exercise
Realize the sequential circuit using EPROM
0
1
0
0
1
1
1
0