Mid3 Revision

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Mid3 Revision
CS147
Lecture 20

• Prof. Sin-Min Lee

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Classification of Digital Circuits

• Combinational.
• Output depends only on current input values.
• Sequential.
• Output depends on current input values and
  present state of the circuit, where the present
  state of the circuit is the current value of the
  devices memory.
• Also called finite state machines.

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State of a Circuit

• The contents of storage elements.
• A collection of know internal signal values that
  contain information about the past necessary to
  account the future behavior of the circuit.

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Clock

• Signal that determines the change of state in
  most sequential circuits.

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S-R Latch With Enable

• The outputs change only when the enable input C
  is asserted.

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S-R Latch With Enable

• Notice that the outputs only change when the
  input C is asserted.

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D Latch

• This latch eliminates the problem that occurs in
  the SR latch when RS0.
• C is an enable input
• When C1 then the output follows the input D and
  the latch is said to be open. Due to this fact
  this latch is also called transparent latch.
• When C0 then the output retains its last value
  and the latch is said to be closed.

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D Latch
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D Latch

• For proper operation the D input must not change
  during a time interval around the falling edge of
  C.
• This time interval is defined by the setup time
  tsetup and the hold time thold .

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Edge Triggered D Flip-Flop

• This flip-flop is made out of two D latches. The
  first latch is the master, and the second the
  slave.
• When CLK_L 1 the master is open (on) and the
  slave is closed (off). Qm and Ds follow Dm .

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Edge Triggered D Flip-Flop

• When CLK_L 0 the master is closed, the slave is
  open and Qm is transferred to Qs . Note that Qs
  does not change if Dm changes because the master
  latch is closed leaving Qm fixed.

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Edge Triggered D Flip-Flop

• Positive edge-triggered D flip-flop.
• Q D

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Edge Triggered D Flip-Flop

• If the set-up and hold times are not met the
  flip-flops output will go to a stable, though
  unpredictable, state.

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Edge Triggered D Flip-Flop

• Asynchronous inputs are used to force the output
  of the flip-flop to a particular state.
• PR (preset) Q 1.
• CLR (clear) Q 0.

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Edge Triggered D Flip-Flop
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Edge Triggered D Flip-Flop

• Edge triggered D flip-flop with enable.

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Scan Flip-Flop

• This flip-flop allows its inputs to be driven
  from alternate sources, which can be very useful
  during device testing.

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Master/Slave S-R Flip-Flop

• The postponed output indicator shows that the
  output signal does not change until the enable C
  input is negated.
• Flip-flops with this kind of behavior are called
  pulse-triggered flip-flops.
• Q SRQ
• SR 0

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Master/Slave S-R Flip-Flop
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Master/Slave J-K Flip-Flop

• The J and the K inputs of the J-K flip-flop are
  analogous to the S and R inputs of the S-R
  flip-flop, except in the case where JK1. In
  this case the outputs of the J-K flip-flop will
  toggle to the opposite state.

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Master/Slave J-K Flip-Flop

• Q JQKQ

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Edge Triggered J-K Flip-Flop

• Q JQKQ

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Edge Triggered J-K Flip-Flop

• 74LS109

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T Flip-Flop

• Flip-flop changes state every tick of the clock.
• Q Q

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T Flip-Flop With Enable

• Flip-flop changes state every tick of the clock
  when enable is asserted.
• Q ENQENQ

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Clocked SynchronousState-Machine Analysis

• State machine Another term for a sequential
  circuit.
• Clocked Refers to the fact that their
  flip-flops employ a clock input.
• Synchronous Same clock signal is used by all
  flip-flops.
• A state machine with n flip-flops can have up to
  2n distinct states.

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State Machine Structure

• State memory a set of n flip-flops.
• Next-state logic combinational logic circuit
  which determines the next state.
• Next-state F(current state,input)
• Output logic combinational logic circuit which
  determines the output.
• There are two models for the output logic
• Mealy Model.
• Moore Model.

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Mealy Model

• The output is based on both current state and
  input.
• Output G(current state,input)

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Moore Model

• The output is based on current state only.
• Output G(current state)
• In high speed circuits the output circuit may be
  absent and the output is generated directly from
  the flip-flops outputs. This is called output
  coded state assignment.

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Mealy Model

• Pipelined outputs a design approach that
  ensures the output of a Mealy model circuit only
  changes with the clock.

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Analysis

• Determine the next-state and output functions F
  and G.
• Use F and G to construct a state/output table
  that completely specifies the next state and
  output of the circuit for every possible
  combination of current state and input.
• Draw a state diagram.

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State Machines With D Flip-Flops

• D0 Q0 EN Q0 EN
• D1 Q1 EN Q1 Q0 EN Q1 Q0 EN

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State Machines With D Flip-Flops

• Q0 D0
• Q1 D1
• Q0 Q0 EN Q0 EN
• Q1 Q1 EN Q1 Q0 EN Q1 Q0 EN

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State Machines With D Flip-Flops

• MAX Q1 Q0 EN

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State Machines With D Flip-Flops

• Q0 Q0 EN Q0 EN
• Q1 Q1 EN Q1 Q0 EN Q1 Q0 EN
• MAX Q1 Q0 EN

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State Machines With D Flip-Flops
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State Machines With D Flip-Flops
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State Machines With D Flip-Flops
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State Machines With J-K Flip-Flops
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Clocked Synchronous State Machine Design

• Derive a state/output table from the problem
  specification.
• Minimize the number of states in the state/output
  table by eliminating equivalent states.
• Choose a set of state variables. Assign to each
  state a unique combination from the set derived
  above.
• Create a transition/output table.
• Choose a flip-flop type and derive its excitation
  table.
• Using the excitation table fill the values for
  the input excitation function columns on the
  transition/output table.
• Derive the excitation and output equations.
• Draw logic diagram.

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Clocked Synchronous State Machine Design

• Design a sequential circuit with one input ( I )
  and one output ( Z )The output is asserted when
  the input sequence 0-1-1 is received.
• See state/output table below.

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Clocked Synchronous State Machine Design

• Set of state variables and their unique
  assignment to the different states.

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Clocked Synchronous State Machine Design

• Transition/output table

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Clocked Synchronous State Machine Design

• Excitation table.

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Clocked Synchronous State Machine Design

• Equations derived from the table above
• J1 IQ0
• K1 IQ0
• J0 IQ1
• K0 IQ1
• Z Q1Q0

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Clocked Synchronous State Machine Design

• Logic diagram.
• J1 IQ0
• K1 IQ0
• J0 IQ1
• K0 IQ1
• Z Q1Q0

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Master-Slave Flip-Flop
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Parallel Registers
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4-Bit Parallel Register
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4-Bit Register With Enable
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Register Files (Simplified)
D and Q are both sets of lines, with the number
of lines equal to the width of each register.
There are often multiple address ports, as well
as additional data ports.
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Memory Devices
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MagneticCoreMemory
Register
Sense wires serve as OR plane.
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SemiconductorMemory
Decoder (AND plane)
OR plane
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Rad-Hard PROM Architecture
No latches in this architecture
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W28C64 EEPROMSimplified Block Diagram
A6-12
A0-5
CE
WE
Latch Enable
OE
CLK
I/O0-7
VW
PE
RSTB
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Our example with flip-flops

• We can use the flip-flops direct inputs to
  initialize them to 0000.
• During the clock cycle, the ALU outputs 0001, but
  this does not affect the flip-flops yet.

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Example continued

• The ALU output is copied into the flip-flops at
  the next positive edge of the clock signal.
• The flip-flops automatically shut off, and no
  new data can be written until the next positive
  clock edge... even though the ALU produces a new
  output.

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Flip-flop variations

• We can make different versions of flip-flops
  based on the D flip-flop, just like we made
  different latches based on the SR latch.
• A JK flip-flop has inputs that act like S and R,
  but the inputs JK11 are used to complement the
  flip-flops current state.
• A T flip-flop can only maintain or complement its
  current state.

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Characteristic tables

• The tables that weve made so far are called
  characteristic tables.
• They show the next state Q(t1) in terms of the
  current state Q(t) and the inputs.
• For simplicity, the control input C is not
  usually listed.
• Again, these tables dont indicate the positive
  edge-triggered behavior of the flip-flops that
  well be using.

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Characteristic equations

• We can also write characteristic equations, where
  the next state Q(t1) is defined in terms of the
  current state Q(t) and inputs.

Q(t1) D
Q(t1) KQ(t) JQ(t)
Q(t1) TQ(t) TQ(t) T ? Q(t)