Development of a High Density Pixel Multichip Module at Fermilab

1
FPGA Testing

• Want to configure an FPGA and read back,
  comparing bit by bit and counting the number of
  errors.
• Bit stream will need to be stored in PTA memory
  clocked via on-board generated clocks - 10 to
  20Mhz with long cable required for Indiana Tests
  (software control of clocks would be too slowup
  to 1.4 hours to configure large device with
  16Mbit bit stream _at_ 3kHz)
• Counters that are readable at any time via
  software include number of bits compared
  counter, 0-gt1 bit errors counter, 1-gt0 bit
  errors counter.
• Use JTAG Boundary-Scan to configure and read back
  (4 signals required)

2
FPGA Testing Conceptual Block Diagram

• 2Mbytes of Memory on PTA CardFPGA under test
  must have lt16M configuration bits.
• Software writes bit stream to PTA memory, writes
  register to begin comparing, then polls the error
  counters to acquire error counts.