Java High Performance Computing Project XSA50 Tutorial

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Java High Performance Computing Project --XSA-50
Tutorial

• Chia-Tien Dan Lo
• Department of Computer Science
• University of Texas at San Antonio

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Objectives

• Shows 2 examples on using XSA-50 board
• An LED decoder
• DIP switch control
• Parallel port control
• A counter that increments number on each second
  tick
• Using clock generator (DS1075)
• Show down the clock

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Prerequisites

• Hardware
• Xess XSA-50 Board
• DC9V Adaptor
• DB25 Cable
• PC
• Software
• Xilinx WebPACK 6.1i
• Xess XSTOOLs

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Spartan II Density
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XSA-50
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What You Can Do

• Configure the following chips
• OSC DS1075 (100MHz 48.7KHz)
• CPLD XC9572XL
• Spartan II XC2S50
• EEPROM AT49F002 (1M bits)
• 8M RAM

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Power the XSA-50

• Two Options
• Plug a DC9V adaptor to J5 (2.1 mm female
  center-positive)
• Using PS/2 power
• Connecting a PS/2 male-to-male cable from the
  Laptop PS/2 port to J4 connector
• Reuse bad PS/2 mice. There are 4 wires (red,
  blue, yellow, white) in the cable. Connect red
  () and blue (-) to get 5V. The other two are
  data and clock which are not used.

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Connection XSA-50 and PC

• Connect a DB25 male-to-male cable between the
  parallel port of a PC and the XSA-50 J8.

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Connection
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XSA-50 Component Arrangement
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Design Flow

• Writing VHDL Code
• Using logic synthesizers to translate VHDL to
  netlist
• Using implementation tools to map logic gates and
  interconnections to FPGAs
• Generating a bitstream
• Programming FPGAs using the bitstream

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LED Decoder
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Outlook
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Starting Project Navigator
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Design

• New a project
• Select device family
• Select HDL
• New a source (right click or project-gtnew source)
• Select I/O ports
• Check VHDL syntax (Synthesize-gtcheck syntax)
• Syntheses (double click synthesize)

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VHDL Code for LED Decoder

• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• use IEEE.STD_LOGIC_ARITH.ALL
• use IEEE.STD_LOGIC_UNSIGNED.ALL
• -- Uncomment the following lines to use the
  declarations that are
• -- provided for instantiating Xilinx primitive
  components.
• --library UNISIM
• --use UNISIM.VComponents.all
• entity leddec is
• Port ( d in std_logic_vector(3 downto 0)
• s out std_logic_vector(6 downto 0))
• end leddec
• architecture Behavioral of leddec is
• begin
• s lt "1110111" when d "0000" else

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Implement Design

• By double clicking implement design, we will map,
  place and route the design into FPGAs

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Check Information

• Resource Usage
• Pin Assignment
• Report for each task

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Constraining the Fit

• The pin assignments have to be redone to reflect
  actual need.

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DIP Switches
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Using Constraint Editor

• Creating a new user constrain file
• Project -gt new source -gt implementation
  constrains file
• Reassign I/O ports
• Double click implement design
• View/Edit Placed Design (FloorPlanner)

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Generating Bitstreams

• Double generate programming file
• A file with bit extension will be created

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Programming FPGAs

• Use GXSLOAD to load the .bit file to Spartan II
  FPGAs
• The first time may not work. Try again!

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Testing

• Use GXSPORT to send data through parallel port.
• Try different DIP switch combination if the
  design takes inputs from them

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Sequential Logic Example - Counter

• Use clock source from DS1075 (100,000,00/2052
  48.7 KHz)
• Use push button (SW2) low-activated
• The counter counts from 0 to 15 and changes
  numbers each second

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VHDL Code for the Counter

• process(reset, slowclk)
• variable cnt integer range 0 to 15
• begin
• if reset '0' then
• cnt 0
• elsif slowclk'event and slowclk '1' then
• cnt cnt 1
• end if
• d lt cnt
• end process
• s lt "1110111" when d 0 else
• "0010010" when d 1 else
• "1011101" when d 2 else
• "1011011" when d 3 else
• "0111010" when d 4 else
• "1101011" when d 5 else
• "1101111" when d 6 else
• "1010010" when d 7 else
• "1111111" when d 8 else

• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• use IEEE.STD_LOGIC_ARITH.ALL
• use IEEE.STD_LOGIC_UNSIGNED.ALL
• entity counter is
• Port ( clk, reset in std_logic
• s out std_logic_vector(6 downto 0))
• end counter
• architecture Behavioral of counter is
• signal d integer range 0 to 15
• signal slowclk std_logic
• begin
• -- slowdown clock
• process(reset, clk)
• variable cnt integer range 0 to 24366
• begin
• if reset '0' then
• cnt 0
• slowclk lt '0'

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Setting DS1073 Frequency

• Disconnect any cable connecting to XSA-50 board
• Change shunt to set on J6 jump
• Start GXSSETCLK tool and set divisor to 2052.
  Then click set.
• Connect cables back to XSA-50

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Pin Assignment

• Connect master clock (clk) to P88 (master_clk)
• Connect reset to P93 (push buton)
• Be careful in the VHDL code that reset should be
  functioned in low state.

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More Information

• http//www.xess.com/manuals/xsa-manual-v1_2.pdf
• http//www.xess.com/appnotes/webpack-5_2-fpga.pdf
• http//toolbox.xilinx.com/docsan/xilinx5/manuals.h
  tm
• ftp//ftp.xilinx.com/pub/documentation/ise5_tutori
  als/ise5tut.pdf