Clock Distribution Based on Both Electrical and Guided Wave Optical Interconnects

1
Clock Distribution Based on Both Electrical and
Guided Wave Optical Interconnects

• Ian Young
• Intel Fellow
• Director Advanced Circuits
• Logic Technology Development
• Hillsboro, Oregon

2
Agenda

• Microprocessor Trends
• Clock Distribution in Microprocessors
• Electrical versus Optical Challenges
• Future Directions for Electrical Clocking
• H-tree Optical Waveguide Design Considerations
• Summary

3
More Transistors per Chip
Microprocessor transistor count
1,000,000,000
Itanium 2 Processor
100,000,000
Pentium 4Processor
Pentium III Processor
10,000,000
Pentium Processor
Pentium II Processor
1,000,000
486 DX Processor
386 Processor
100,000
286
8086
10,000
4004
8080
8008
1,000
1970
1980
1990
2000
2010
1B transistor microprocessor by 2007
4
Faster Devices
MHz
Microprocessor Clock Frequency
10,000
Pentium 4 Processor
1,000
Pentium II Processor
Pentium III Processor
486 Processor
100
Pentium Processor
286
386 Processor
10
8085
8086
4004
1
8080
0.1
1970
1980
1990
2000
2010
Microprocessor clock frequency trending to
10GHz by 2007
5
Higher Performance, Lower Cost
MIPS
Pentium 4 Processor
10000
Pentium III Processor
Pentium II Processor
1000
Pentium Pro Processor
100
Pentium Processor
Intel486TM DX CPU Microprocessor
10
Intel386TM DXMicroprocessor
MIPS
1
1985
1989
1993
1995
1997
1999
2001
1991
1987
6
Interconnect Delay Challenge
Signal Transmission Delay (43 µm line)
100
Low K ILD
Al SiO2
Cu Air
10
Delay (ps)
Gate Delay
1
90nm
65nm
45nm
30nm
0.1
100
1000
10
Technology Generation (nm)
Need process, circuit design and architectural
innovations
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Processor Core and I/O Bus Clock Frequency
3500
Core Clk
3000
Bus Clk
2500
2000
Clock Frequency (MHz)
1500
1000
500
0
386
P-100
P-150
P-200
486-33
PII-300
PIII-1G
486DX2
486DX4
PIII-600
PIII-800
P4-1.5G
P4-2.0G
P4-2.5G
P4-3.0G
Processor

• Core frequency continues to increase with each
  generation
• Bus frequency is not keeping up with the
  processor core

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Why a Clock?

• Synchronous Logic
• Logic progresses at a rate controlled by the
  clock
• Retiming removes the effects of different logic
  and wire delays
• Slows down signals that arrive too fast
• Requires a state element
• Latch stores input when clock is low
• Flip-Flop stores input when clock rises
• Enables CPU pipelining and high through-put CPUs

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Latches vs Flip-Flops

• Clocks work with Latches or Flip-Flops to hold
  state
• Latch
• Stores data when the clock is low
• Delay Td-q
• Flip-Flop
• Stores In when clock rises
• Delay Tsetup Tclk-q

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Master-Slave Flip-Flop
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Flip-Flop Set-up and Hold Times

• Setup Time
• time before the clock signal, that a data signal
  must be valid in order to be stored.
• Hold Time
• time after the clock signal, that a data signal
  must be valid in order to be stored.

Setup time
Data In
Clock
Hold time
Data Out
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The Clock Distribution Problem

• Deliver the clock signal from the source (PLL) to
  all the receivers with the best timing precision.
  
• CLOCK SKEW is the inaccuracy of the same clock
  edge arriving at various locations in the chip
  (spatial separation)
• CLOCK JITTER is the inaccuracy of consecutive
  clock edges arriving at the same location
  (temporal separation)

PLL
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Clock and Logic Structure Operation

Clock Delay 1 delay from Clock to the Clock
input of U1. Clock Delay 2 delay from Clock to
the Clock input of U2. Clock Skew Clock Delay 2
Clock Delay 1 (should be zero).
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SETUP violation Data arrives at U2 too late,
anddoesnt get captured by U2 clock cycle.
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HOLD violation Data arrives at U2 too soon, not
held long enough to be captured by U2 clock cycle.
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Agenda

• Microprocessor Trends
• Clock Distribution in Microprocessors
• Future Directions for Electrical Clocking
• Electrical versus Optical Challenges
• H-tree Optical Waveguide Design Considerations
• Summary

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Challenges for Clock Design

• Rapid increases in Core Clock Frequencies
• 1991 100 MHz (0.8mm)
• 1997 400 MHz (0.35mm)
• 2001 2.0GHz (0.13mm)
• Increasing Clock Load
• as indicated by total transistors/die
• 1991 1.2 million transistors (0.8mm)
• 1997 7.5 million transistors (0.35mm)
• 2001 42 million transistors (0.13mm)
• Worsening within-die process variations
• Lithography and Etch
• Supply Noise
• Hot Spots within die

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Electrical Clocking (Present)
Processor
Clk Tree
100MHz
PLL (4 GHz)
2.0 GHz
Bus
PLL
Clock generator/ buffer
400 MT/s
Crystal (10 MHz)
Chipset
100MHz
66 MHz
PLL
(500MHz)
66 MHz chip
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Clock Distribution H-Tree (2 level)
Global / LocalSkew
L1
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Design Challenges

• Clock distribution network delay across the die
  is increasing
• Clock network delay is multiples of the the clock
  period
• Signal propagation across the die is multiples of
  the clock period
• Clock distribution bandwidth
• Higher than the nominal clock frequency
• Global skew is increasing
• But the region of clock influence for high
  frequency is decreasing
• Logic Path distance reducing
• di/dt induced power supply noise modulates the
  clock buffer delay
• Creates cycle-to-cycle jitter

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Design Considerations

• Power due to the nodes toggled by clock is
  increasing
• Pentium II 40 of total chip power
• Pentium 4 60 of total chip power
• Clock distribution power is still 10-15 of total
  chip power
• Majority of the clock power is consumed by the FF
  and its local buffers
• Clock distribution bandwidth must be higher than
  the nominal clock frequency
• di/dt induced power supply noise modulates the
  clock buffer delay
• Creates cycle-to-cycle jitter
• Global skew is increasing but may not be a
  problem
• Logic path distance reducing
• The region of low skew clock influence for the
  highest frequency is decreasing
• Controlled skew can actually be used to enhance
  the operating frequency (cycle time borrowing)

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Agenda

• Microprocessor Trends
• Clock Distribution in Microprocessors
• Future Directions for Electrical Clocking
• Electrical versus Optical Challenges
• H-tree Optical Waveguide Design Considerations
• Summary

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Future Electrical Directions

• Designers will push frequency clock higher
• Drives Performance! gt10GHz in 5years / 40GHz in
  10years
• Clocking systems will continue to evolve with
  more complex electrical methods
• Skew tuning and active feedback clock de-skewing
  circuit complexity will increase.
• Design the clock distribution will be much more
  complex
• Design the micro-architecture with interconnect
  delay and clock skew comprehended
• Exploit locality for frequency scaling
• Logic clock domains
• Clock Distribution Power will take a larger of
  the total chip power

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Agenda

• Microprocessor Trends
• Clock Distribution in Microprocessors
• Future Directions for Electrical Clocking
• Electrical versus Optical Challenges
• H-tree Optical Waveguide Design Considerations
• Summary

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Clock Distribution System Challenges
Optical and Electrical clocking schemes have
advantages for different system challenges
Electrical
Optical

• Large bandwidth independent of distance
• Need DUTY CYCLE - 50
• JITTER gt 12 ps long term demonstrated
• 5ps for 10GHz
• 2.5ps for 20GHz
• Optical Laser stability
• Only at optical detector loop
• SKEW over DISTANCE gt Optical has no skew using
  equal distant branches of H-tree
• WITHIN-DIE VARIATIONS
• TIA Transistor
• Interconnect Waveguide, photodetector
• Temperature optical component dependence
• EMI Insensitive to EMI
• POWER May require large external power for laser

• FREQUENCY dependent on DISTANCE
• Need DUTY CYCLE - 50
• JITTER
• Cycle to Cycle lt 5 of period
• Long term lt 10 of period
• Power supply noise component
• Inductance
• SKEW dependent on DISTANCE
• 5 to 22 Tcycle (local to global)
• WITHIN-DIE VARIATIONS
• Transistor
• Interconnect R, C, L
• Temperature - electrical component dependence
• EMI
• POWER on-chip power requirement

Ref. Peter J.Delfyett et al, J. of Lightwave
Technology, Vol. 9 (12), 1646
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Agenda

• Microprocessor Trends
• Clock Distribution in Microprocessors
• Future Directions for Electrical Clocking
• Electrical versus Optical Challenges
• H-tree Optical Waveguide Design Considerations
• Summary

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Optical Clocking (Future)
H Tree
an optical receiver,
local electricalH-tree
Processor
10GHz Laser
Optical Clock Distribution Waveguide corner,
splitter, etc.
system clk gen
Bus
2 GT/s
source synchronous
Chipset
200MHz
50MHz
PLL
(1GHz)
66 MHz chip
ref clock
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Waveguide Propagation Splitting Loss for
Optical Clock Trees
loss /split
1 cm
1 cm

• For 1x128 H-tree distribution optical clock -the
  total length of a single waveguide is 1 cm for
  a 1 cm x 1cm die. The waveguide is split 7 times.

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Speculative Optical Clocking H-Tree
Loss per distance -1dB/cm
Loss per bending 0.25 dB
Insertion loss 1.5 dB
Loss at split 1 dB/per split
4 nodes
16 nodes
Loss per H-Tree (2 splits, halving per split 3
dB/cm, so - 6 dB/cm per H-Tree)
64 nodes
With 10 mW input optical power 20uW optical power
at nodes
Total loss
256 nodes
1024 nodes
We may need 100 mW laser in order to have 256
nodes H-Tree
We may not need 1024 node for on-Chip clocking
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Conclusions

• Many technology issues for Optical Clocking
• The frequency requirements are high.
• Power efficiency and uniformity of optical clock
  distribution is challenging.
• Need to start working to understand the optical
  technology breakthroughs for the microprocessor
• Electrical Clocking will continue to innovate
• Electrical clocking will achieve 10GHz in 5years
• 40GHz ??
• Need to watch this and identify the right
  intercept for Optical