Realtime Simulation: Using VTB with DSP Processor Arrays

1
Realtime Simulation Using VTB with DSP
Processor Arrays
Real-Time Power Electronics Simulation
Roy Crosbie, John Zenor, Dick Bednar, Dale
Word California State University, Chico Nari
Hingorani Consultant

• VTB 2004 Users and Developers Conference
• University of South Carolina September 14-15, 2004

2
Overview

• DSP Based Simulation Engine
• TigerSharc Performance
• Hardware in the Loop Configuration
• Automated Model Development
• VTB Back to Back Converter Model
• Other VTB Model Integration Efforts

3
DSP Based SimulationsOverall Goals

• Develop a representative set of back-to-back
  system models with lt 10 µsec frame times
• Base user interface on VTB/VXE
• Further reduce frame times to support
  higher-frequency PWM models
• Implement simulations with hardware in the loop
  using both digital to analog and digital to
  digital interfaces
• Develop techniques for partitioning models into
  modules capable of combination with other modules
  or hardware
• Develop scalable techniques that allow more
  complex simulations without increasing frame
  times

4
DSP Based SimulationsDesign Criteria

• Low Cost, Commercially Available Solutions
• Conventional desk-top PC host running VTB/VXE
• PCI boards with small, expandable, DSP arrays
• Scalability
• Multiple boards in same host
• Multiple PC hosts

5
DSP Simulation Platform Architecture
6
VTB Integration

• VTB as Control Interface, VXE as Graphical
  Display
• Execution Sequence
• VTB used to start application, presenting
  configuration and control interface
• Simulation Starts - Parameters loaded to DSP
  board via PCI bus
• Simulation Runs
• Real Time on DSP boards, with results passed to
  VTB via PCI bus
• Non-Real Time on PC, running on host CPU
• VXE displays graphical results, updating display
  with every block of data received from DSP board

7
Performance
8
TigerSharc Data Transfer Issues

• Link Ports Between DSPs
• Single vs Dual Link Ports
• Bidirectional vs Unidirectional
• DMA Transfer Engine Differences
• Different configuration/control interface
• Host Interface Differences
• Complete rework of PCI bus/DMA interface
• Processor Synchronization Mechanisms
• No Messenger Registers
• Use of shared internal memory to synchronize

9
Scheduling Considerations

• Load Leveling Across DSP Processors
• Faster Numerical Operations
• Link Port I/O Proportional to Clock Rate
• Other I/O Relatively Constant
• TS101 Processor Architecture Differences
• Additional ALUs (4 vs 2)
• Will utilize once load leveling done.

10
Scalability
11
Further Refinement to Algorithms for Partitioned
Models
12
Hardware in the Loop Architecture

• Real-Time Linux Based AC System Simulator
• Generator Model
• 3 Current Inputs, 3 Phase Outputs
• External Control
• Transtech DSP Board Executing Controller
• Connection Via External Link Port

13
Hardware in the Loop
14
Hardware in the Loop

• Asynchronous Operation
• Distinct Time Frames
• Generator Simulation (Real Time Linux) 10s of µs
• Simulation Engine (DSP Board) lt 10 µs
• Digital Control Interface Options
• Link Port Conversion
• FPGA Based Design

15
Digital and Analog Interfaces

• Analog I/O Performance Penalty
• A/D Conversion
• Digital I/O Conversion
• Link Port Board Modifications
• Data rate
• 8 bit data transfers (vs 4 bit previously)
• Protocols
• Directional negotiation
• Heartbeat function

16
Model Development Process

• Stages in the process of Model Development
• Circuit Diagram or Differential Equation
  Specification
• Differential Equations in standard vector form
• Difference Equations incorporating integration
  algorithm
• C code implementation

17
Automated Software Development

• Goals The goal of the automated software
  development effort is to provide a more rapid and
  error-free process for converting specifications
  of new models into executable real-time code.
• Sequence The process of developing executable
  code has three main phases.
• Convert the model specification (circuit diagram
  or differential equation based) into a set of
  differential equations in standard vector form
  (SVF)
• Combine the SVF equations with the numerical
  integration algorithm to produce a set of
  difference equations
• Convert the difference equations into executable
  code and merge it into an executable program.

18
Automated Software Development
19
VTB Component Model6 Pulse Back to Back
Converter

• Standalone Model
• Only 2 Connection Points
• Total Power for Left and Right Sides
• Graphical Analysis of Converter Behavior
• Varying Parameter Sets

20
Back to Back Converter Component Diagram
21
Detailed Circuit Diagram and Parameter List
22
Graphical Output
23
VTB Integration Steps

• Integration levels
• Access to RTPS models through VTB user interface.
  Graphical output via VXE. Parameter changes
  allowed during simulation run.
• Combined simulation using non real-time versions
  of RTPS and VTB models.
• Decompose 6 Pulse BTB Model into Component parts
• Integrate Components into VTB Framework
• Future Combined simulation using real-time
  versions of RTPS and VTB models.