Introduction to VHDL

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Introduction to VHDL
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Entity

• Describes all inputs and outputs
• Every VHDL design must has at least one entity
• Requires the use of Identifiers for naming the
  entity itself as well as the inputs and outputs
• Entity is a keyword and is reserved in VHDL for
  this purpose

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Identifiers

• User defined names used to identify VHDL elements
  and units
• Two types of identifiers
• Basic identifiers
• Extended identifiers

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• A basic identifier consists only of lowercase
  letters or uppercase letters, numeric digits and
  single underscores. Upper and lower case can be
  mixed
• A letter must be used as the first symbol in an
  identifier name
• Basic identifiers must not contain spaces
• VHDL Keywords or reserved identifiers may not be
  used as identifiers
• Appendix X lists VHDL keywords and reserved
  identifiers

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Entity declaration
entity ltentity identifiergt is port (signal
identifier) end entity ltentity identifiergt
entity OR_1 is port (A,B in bit X out
bit) end entity OR_1
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Port Statement

• A port is an input or output signal
• port is a VHDL keyword
• The port statement must specify the port
  identifier, the port direction, and the port data
  type
• 3 port directions in, out, inout
• Many data types one of which is bit
• bit has two values, 0 and 1

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port (A, B in bit X out bit)

• Two input ports A and B
• One output port X
• Port assignments are enclosed by parentheses
• Port statement ends with a
• Direction of port is in or out
• Bit is the data type

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Data Types
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Architecture

• Architecture declaration is where the operation
  of the logic function is specified
• For each entity there must be a corresponding
  architecture
• Each architecture must be associated by name with
  an entity

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architecture lt architecture namegt of ltentity
namegt is begin The description of the logic
function goes here end architecture ltarchitecture
name
architecture ORfunction of OR_1 is begin X lt A
or B end architecture ORfunction
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Program for 2-input OR gate
-- Program for 2-input OR gate entity OR_1
is port (A,B in bit X out bit) end entity
OR_1 architecture ORfunction of OR_1 is Begin
X lt A or B end architecture ORfunction
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Programming

• VHDL comments are proceeded by two dashes - -
• Data flow descriptions
• X lt A data associated with A is assigned to X
• Behavioral description is used when a logic
  function is too complex for data flow approach
• X lt1 when (A0) else 1

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Logical Operators
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Program for 3-input AND gate
-- program for 3-input AND gate entity AND_gate
is port (A, B, C, in bit X out bit) end
entity AND_gate architecture ANDfunction of
AND_gate is Begin X lt A and B and C end
architecture ANDfunction
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VHDL Bit Vectors and Arrays

• bit_vector data type allows the grouping of bits
  in an array
• An array is a set of individual items with a
  single name
• Each item of the array has an identifier name and
  a numerical index
• If A were the identifier of a bit vector the A(0)
  would be the first item in the array and A(1)
  would be the second item of the array
• Port(A in bit_vector(0 to 7)) would be a input
  port with 8 inputs A(0), A(1), A(2), A(7)

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Binary to 7 segment display decoder
A(0) A(1) A(2) A(3)
X(0) X(1) X(2) X(3) X(4) X(5) X(6)
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Binary to 7 segment display decoder using data
flow approach
entity Binary_to_seven_segment is port( A
in bit_vector(0 to 3) X out bit_vector(0 to
6)) end entity Binary_to_seven_segment
architecture decoder of Binary_to_seven_segment
is Begin X(0) lt (not A(0) and not A(2)) or (not
A(0) and A(3)) or (A(1) and not A(3)) or (A(1)
and A(2)) or (A(0) and A(2) and not A(3)) or (not
A(1) and not A(2) and A(3)) X(1)lt (not A(0) and
not A(2)) or (not A(1) and not A(2)) or (not A(0)
and not A(1) and not A(3)) or (A(0) and A(1) and
not A(3)) or (A(0) and not A(1) and A(3))
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Binary to 7 segment display decoder using data
flow approach continued
X(2)lt (not A(2) and A(3)) or (A(2) and not A(3))
or (not A(1) and not A(2)) or (A(0) and not A(2))
or (A(0) and not A(1)) X(3) lt (not A(1) and
A(3)) or (A(0) and not A(2) and A(3)) or (A(0)
and not A(1) and A(2)) or (not A(0) and A(1) and
A(2)) or (not A(0) and not A(2) and not A(3)) or
(A(1) and not A(2) and not A(3)) X(4) lt (not
A(0) and not A(2)) or (A(2) and A(3)) or (not
A(0) and A(1)) or (A(1) and A(3))
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Binary to 7 segment display decoder using data
flow approach continued

• X(5) lt (not A(2) and A(3)) or (not A(0) and not
  A(1)) or (not A(0) and A(2)) or (A(1) and A(3))
  or (not A(1) and A(2) and not A(3))
• X(6) lt (not A(1) and not A(2) and not A(3)) or
  (not A(0) and not A(1) and A(2) and A(3)) or
  (A(0) and A(1) and A(2) and not A(3))
• end architecture decoder

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-- Full adder data flow approach.
entity FULLADDER is port (X in bit Y in
bit Cin in bit Cout out bit Sum
out bit) end FULLADDER architecture
full_adder_logic of FULLADDER is begin Sum lt
X xor Y xor Cin Cout lt (X and Y) or (X and
Cin) or (Y and Cin) end full_adder_logic
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4 bit Full adder with Integers
entity FULLADDER is port (X, Y in integer
range 0 to 15 Cin in integer range 0 to
1 Sum out integer range 0 to 31) end
FULLADDER architecture full_adder_logic of
FULLADDER is begin Sum lt X Y Cin end
full_adder_logic
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Conditional Statements

• if
• if-then-else
• elsif
• case

Events processing inside a VHDL program allows
for programs statements to be concurrent or
sequential. Conditional statements allow VHDL
programs to respond to events that may occur.
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If statement

• Causes a decision to be made
• When the if statement is true the code following
  the if statement is executed
• When the if statement is false the code following
  the if statement until the end if is skipped

if conditional statement then VHDL
statements end if
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If-Then-Else statement

• else is an alternative path for the if statement

if conditional statement then VHDL
statements else VHDL statements end if
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Elsif statement

• Use to allow multiple alternative paths

if conditional statement then VHDL
statements elsif conditional statement then
VHDL statements elsif conditional statement
then VHDL statements end if
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Case Statement

• Similar to a nested if statement
• Case statement must account for all possible
  outcomes
• VHDL keyword others can be used to account for
  remaining outcomes but is not required

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Case statement example
case expression is when choice gt VHDL
statement when choice gt VHDL statement
when others gt VHDL statements end case
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Functions and Procedures

• Types of subprograms in VHDL
• Allow for modularization and code reuse
• process can also be used as a subprogram
• A function is a subprogram that operates on a set
  of inputs and returns an output
• A procedure is a subroutine that operates on an
  argument list and passes values back through the
  argument list
• function and procedure will require a call

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Function example
function and_gate (X, Y in bit) return bit
is begin return X and Y end and_gate
To call a function AND1 xltand_gate (A,B)
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Procedure example
procedure or_gate(X, Y in bit OUT out bit)
is begin OUT lt X or Y end or_gate
To call a procedure B1 or_gate (AgtX, BgtY, OUT
gtV1)
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Libraries, Packages and Package Bodies

• VHDL provides for the development of package
• They hold commonly-used elements
• Procedures and functions are in packages
• Packages can be user defined or vendor supplied
• Libraries are used to hold packages

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Libraries

• Two types
• Standard libraries
• User defined
• IEEE Standard Library

VHDL library coding library ieee use
ieee.std_logic_1164.all use ieee.std_logic_1164.s
td_logic
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Packages

• Used to hold reusable code
• Components
• Functions
• procedures

Package declaration package user_defined_name is
package declarations end package
user_defined_name
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Package Body

• Only packages with a subprogram require a package
  body

Package body example package body
user_define_name is package body
definitions End package body user_defined_name
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Loops

• A loop repeatedly executes the sequential
  statements contained within the loop structure
• for loop
• Entry point
• Iteration
• terminal test

for identifier in starting value to stopping
value loop VHDL statements end loop
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While loop

• A for loop stops after a fix number of iterations
• A while loop continues to loop until a condition
  is met
• Structure
• Entry point
• Terminal test
• Exit point

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While loop general form
while Boolean expression loop VHDL
statements end loop