Development of a System-On-Chip Extensible Network Processor and debugging using Identify

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Development of a System-On-Chip Extensible
Network Processor and debugging using Identify

• John W. Lockwood
• and Chris Zuver
• Applied Research Laboratory Reconfigurable
  Network Group
• http//www.arl.wustl.edu/projects/fpx/reconfig.htm
  
• lockwood_at_arl.wustl.edu
• cz2_at_arl.wustl.edu

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FPX Hardware Platform
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FPX Hardware in WUGS-20 Switch
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FPX Hardware in GVS-1000 Chassis
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System-On-Chip Firewall
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Content Matching Module
regex_app (given)
dataen_out_appl d_out_appl sof_out_appl eof_out_a
ppl sod_out_appl tca_out_appl clk reset_l enable
_l
dataen_appl_in d_appl_in sof_appl_in eof_appl_in s
od_appl_in tca_appl_in Matched ready_l
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From Protocol Wrappers
To existing MP1 circuit
To extended Bits of CAM
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wrapper_module.vhd
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Packet matching w/ Content Addressable Memory

• Sample Packet
• Source Address 128.252.5.5 (dotted.decimal)
• Destination Address 141.142.2.2
  (dotted.decimal)
• Source Port 4096 (decimal)
• Destination Port 80 (decimal)
• Protocol TCP (6)
• Payload Consolidate your loans. CALL NOW
• Payload Lists General SPAM (0), Save Money
  SPAM (1)
• Content Vector 00000011 (binary) x03 (hex)

111
104
7
103
39
71
8
40
0
72
Dest IP (hex) 8D8E0202
Src IP (hex) 80FC0505
SrcPort 1000
Dest Port 0050
Proto 06
All values shown In hex
Con- tent 03
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Sample Filter

• Source Address 128.252.0.0 / 16
• Destination Address 141.142.0.0 / 16
• Source Port Dont Care
• Destination Port 80
• Protocol TCP (6)
• Payload includes general SPAM (List 0)

Src IP value 80FC0000
Dest IP (hex) 8D8E0000
SrcPort 0000
Dest Port 50
Proto 06
Con- ten t 01
Value
Mask 1care 0dont care
Src IP (hex) FFFF0000
Dest IP (hex) FFFF0000
SrcPort 0000
Dest Port FFFF
Proto FF
Con- ten t 01
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103
39
71
8
40
0
72
Dest IP (hex) 8D8E0202
Src IP (hex) 80FC0505
SrcPort 1000
Dest Port 0050
Proto 06
Con- tent 03
IP Packet
DROP the packet It matches the filter
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Packet Classifier with FlowID
112 bits
16 bits
Flow ID 1
CAM MASK 1
CAM VALUE 1
Flow ID 2
CAM MASK 2
CAM VALUE 2
16 bits
- - CAM Table - -
Flow ID
Flow ID 3
CAM MASK 3
CAM VALUE 3
. . .
Resulting Flow Identifier
. . .
. . .
Flow ID N
CAM MASK N
CAM VALUE N
Bits in IP Header
Flow List
Priority Encoder
Source Port
Protocol
Payload Match Bits
Mask Matchers
Dest. Port
Value Comparators
Source Address
Destination Address
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Other Modules Implemented

• IPv4 CAM Filter
• 104 Bit header matching
• Fast IP Lookup (FIPL)
• Longest Prefix Match
• MAE-West at 10M pkts/second
• Packet Content Scanner
• Reg. Expression Search
• Data Queueing
• Per-flow queue in SDRAM

• IPv6 Tunneling Module
• Tunnels IPv6 over IPv4
• Statistics Module
• Event counter
• Traffic Generator
• Per-flow mixing
• Video Recoder
• Motion JPEG
• Embedded Processor
• KCPSM

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Use of Identify in the FPX Design Flow

• Identify is natural additional to the current
  design flow
• Adds two new steps
• Instrument
• Debug

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Two Part Solution

• Instrumenter
• Assigns signals to monitor/trigger
• Modifies existing VHDL
• Does not change original vhdl (create copies)
• Streamlines synthesis
• Debugger
• Communications to hardware via JTAG
• Uses trigger setup
• Includes waveform viewer
• Creates VHDL simulation model

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Instrumenter Step 1

• Import Synplicity Project File
• File gtgt Import Synplicty Project .

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(No Transcript)
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Instrumenter Step 2

• Choose Signals to Monitor
• Right-click glasses symbol near signal to
• Sample and Trigger
• Sample Only
• Trigger Only

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Instrumenter Step 3

• Set Options
• Click Edit IICE Options

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Device Family
JTAG port Builtin Using RJ-45 Port on FPX Syn
Adds four JTAG I/O to toplevel (map rad_test)
Name of Clock in VHDL
Physical Resource Usage
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BufferType Deviceram Block RAM Logic
Flip-Flops
Number of Sample (Trade-Off Resources)
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Triggering Options Self-Explanatory
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Instrumenter Step 4

• INSTRUMENT DESIGN
• Click Save and Instrument Current Project

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Synthesis

• Open Synplicty
• RUN gtgt Run TCL Script
• Locate Synplicity.tcl in syn_projectname folder

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Synthesis
VHDL Files Containing Instrumented Design
Synplicity Synthesis Directory (.edf file here
after running Synthesis)
TCL Script for Importing to Synplicity
Note New Directory created by Instrumenter in
Folder where imported Synplicity Project is
located
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Continue Design Flow

• Add .edf file to build directory
• Generate Bitfile like usual
• Load Bitfile to FPX using NCHARGE
• Make sure JTAG cable is unplugged
• Connect JTAG Cable to FPX and PC running IDENTIFY
  (Parrallel JTAG)
• Open IDENTIFY Debugger

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IDENTIFY DEBUGGER

• File gtgt Open Project
• Locate the Instrumenter Project File
• Should be in same directory as Synplicity Project
  file

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IDENTIFY DEBUGGER

• Trigger
• Locate and set Trigger Event
• Right Click Signal

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IDENTIFY DEBUGGER

• Setup Project Options

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IDENTIFY DEBUGGER
Xilinx JTAG Cable
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IDENTIFY DEBUGGER
RUN
Waveform
STOP
Locate Trigger Signals
Relative Trigger Event (Trigger Beginning,
Middle, End of Sample)
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IDENTIFY DEBUGGER

• Waveform

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IDENTIFY DEBUGGER

• RTL View

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References

• Debugging of an Internet Packet Scheduler Using
  the Identify Software, by Christopher K. Zuver
  and John W. Lockwood, The Syndicated, Volume 4,
  Issue 4, 2004.
• An Extensible, System-On-Programmable-Chip,
  Content-Aware Internet Firewall, by John W.
  Lockwood, Christopher Neely, Christopher Zuver,
  James Moscola, Sarang Dharmapurikar, and David
  Lim Field Programmable Logic and Applications
  (FPL), Lisbon, Portugal, pp. 859-868 (Paper 14B),
  Sep 1-3, 2003.
• Automated Tools to Implement and Test Internet
  Systems in Reconfigurable Hardware, by John W.
  Lockwood, Chris Neely, Chris Zuver, Dave Lim
  SIGCOMM Computer Communications Review (CCR), vol
  33, no 3, July 2003, pp 103-110.