Design of a 10GHz Clock Distribution Using Coupled StandingWave Oscillators

1
Design of a 10GHz Clock Distribution Using
Coupled Standing-Wave Oscillators

• Frank OMahony1, C. Patrick Yue2, Mark Horowitz1,
  S. Simon Wong1
• 1Stanford University, Stanford, CA
• 2Aeluros, Inc., Mountain View, CA

2
Outline

• Motivation
• Introduction to standing waves
• Standing-wave oscillator
• Standing-wave clock grid
• Measurement setup and results
• Conclusions

3
Motivation

• Problem MPU global clock distribution is not
  scaling
• Frequency increases, timing uncertainty must
  decrease
• 10GHz MPU clocks within the next 5-10 years
• Skew and jitter increase with clock latency
• Long wire performance is getting worse
• Solution Coupled standing-wave oscillators
• Standing wave / Salphasic low skew
• Coupled oscillators reduced skew and jitter
• Compatible with digital layout

4
Travelling Waves
Incident wave
Zo
5
Travelling Waves
Incident wave
Zo
6
Travelling Waves
Incident wave
Zo

• Wave characteristics
• Phase varies linearly with position
• Amplitude is constant with position

7
Standing Waves
ZL 0 (?L -1)
8
Standing Waves
Reflected wave
9
Standing Waves
Reflected wave
10
Standing Waves
Reflected wave
11
Standing Waves
Standing wave
12
Standing Waves
Standing wave
13
Standing Waves
Standing wave
14
Standing Waves
Standing wave
15
Standing Waves
Standing wave
16
Standing Waves
Standing wave
17
Standing Waves
Standing wave
18
Standing Waves
Standing wave

• Wave characteristics
• Phase is constant with position (with 180º
  discontinuities)
• Amplitude varies sinusoidally with position

19
Standing Waves on Lossy Wires
Incident wave
Attenuated reflected wave


Residual travelling wave
Standing wave

• Wire loss causes skew
• Design using low-loss, inductive wires

20
Distributing Gain Along Wires
-gd
-gd
-gd
-gd
transconductance per unit length
Cross-coupled NMOS pair
-gd
cd
21
Standing-Wave Oscillator (SWO)
LC oscillator
Standing-wave oscillator
Tank
Gain
?/2
22
SWO Coupling
Icouple

• Couple by directly connecting the wires
• Low-Q oscillators have wide locking range

23
SWO Injection Locking
Clkinj
Iinject

• Injection lock to an external clock source

24
SWO Clock Grid
25
SWO Clock Grid
26
SWO Clock Grid
27
SWO Clock Grid
28
SWO Clock Grid
Clkinj
29
SWO Clock Grid Waveform
t (0/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
30
SWO Clock Grid Waveform
t (1/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
31
SWO Clock Grid Waveform
t (2/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
32
SWO Clock Grid Waveform
t (3/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
33
SWO Clock Grid Waveform
t (4/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
34
SWO Clock Grid Waveform
t (5/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
35
SWO Clock Grid Waveform
t (6/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
36
SWO Clock Grid Waveform
t (7/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
37
SWO Clock Grid Waveform
t (8/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
38
SWO Clock Grid Waveform
t (9/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
39
SWO Clock Grid Waveform
t (10/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
40
SWO Clock Grid Waveform
t (11/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
41
SWO Clock Grid Waveform
t (12/12)Tclk
Voltage (arbitrary units)
Y (wavelengths)
X (wavelengths)
42
Phase Properties of Coupled SWOs
Clkinj
43
Jitter for SWO Grids
ps
fclk10GHz
ps
ps
Vdd
0.9Vdd
tf1/fclk
44
10GHz Clock Grid Test Chip
14 µm
14 µm
3.5µm
4 µm
Clkinj
90µm/0.18µm
ccp
0.6mm
1.8mm
Accumulation-mode MOS varactor
ccp

• Fabricated in a 0.18µm 1.8V 6M CMOS process

ccp
ccp
ccp
l 3.0mm
45
Clock Grid Tuning Range

• Tune grid using 150µm/0.54µm accumulation-mode
  MOS varactors
• 300fF 800fF per varactor

46
Skew Measurement Technique
cos(?t ?1)
cos(?t ?2)
41
cos(?t ?3)
cos(?t ?4)
cos(?x - ?ref)
cos(?t ?ref)

• Homodyne technique mixes phase down to DC
• Multiplexing signals to the same mixer minimizes
  measurement errors due to mismatch

47
Skew Measurement Technique
?ref
Voltmeter
chip boundary
Clkinj
48
Skew Measurements

• Tuned grid
• 0.6ps global skew

49
Skew Measurements

• Tuned grid
• 0.6ps global skew
• Skewed grid
• Detune half grid

Detune to 10.1GHz
50
Skew Measurements

• Tuned grid
• 0.6ps global skew
• Skewed grid
• Detune half grid
• 3.3ps global skew
• 1.4ps local skew

51
Jitter Measurements
1.4ps-rms
SWO clock grid
CLKref
1.5ps-rms
52
Die Micrograph
3.0mm
Open-drain buffer
Differential transmission line
MUX and Mixer
53
Clock Buffer
Clk
Clk
Vin
Sine-to-square converter
Limiting Amplifier and LPF

• Buffer delay must be invariant to input amplitude
• Use low Vod in differential pairs for fast
  switching
• Filter harmonics from limiting amplifier

54
Clock Buffer Performance
Clock input
200mV
140mV
5.9ps skew (1.2 of clock cycle)
Clock output
55
Conclusions

• A 10GHz standing-wave clock grid is integrated in
  a 0.18µm standard CMOS process.
• Low-skew standing waves can be sustained using
  lossy on-chip interconnects and distributed gain.
• Multiple standing-wave oscillators can be coupled
  and injection locked to form a clock grid.
• Standing-wave clock grids have low skew and
  jitter.
• Standing-wave global clock distribution is an
  attractive alternative for 10GHz clocking and
  beyond.

56
Acknowledgements

• MARCO Interconnect Focus Center and Intel Ph.D.
  Fellowship Program for funding
• TSMC for chip fabrication
• K. Soumyanath and M. Anders at Intel
• R. Chang, N. Talwalkar, B. Kleveland,
  T.Soorapanth at Stanford University