Automated Clock Distribution With Variable FlipFlop Selection And Voltage Domains

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Automated Clock Distribution With Variable
Flip-Flop Selection And Voltage Domains

• Fred Chen
• Professor Robert W. Brodersen
• Professor Borivoje Nikolic
• Dept. of EECS
• University of California, Berkeley
• January, 2000

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Motivation

• Design Reliability
• Chip Failures are Often Due to Timing Problems
• A Proven Automated Design Can Reduce Chip
  Failures
• A Need In Automated Design Flow
• Automation Allows a High Level Designer To Make
  System Level Changes and Verify the Design
  Without Having to Tweak the Clock Network Every
  Time a Change is Made at the System Level
• Reduction in Design Time
• Even if the Synthesized Clock Net is Not
  Satisfactory to the Designer, it Provides a Good
  First Pass at the Clock Tree
• Design Flexibility
• Support of Variable Flip-Flops Voltages Allows
  Flexibility For Lower Power and/or Better
  Performance Designs

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Clock Tree Concerns(If we did it by hand)

• Constraints for Functionality
• Clock Skew Issues
• Setup/Hold Constraints for Different FFs _at_
  different voltages are different.
• Clock Edges (Rise/Fall Times) Affect Flip-Flop
  Setup/Hold Times
• Matching Wire lengths, Process Variations, IR
  drops
• Insertion Delay

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Clock Tree Concerns (Cont.)

• Performance Needs
• Power/Energy Consumption
• Speed, Robustness
• Methodology to Meet Constraints
• System Single Phase, 2-Phase, Synchronous,
  Asynchronous, Globally Asynch. Locally Synch.,
  Skew Compensating Circuitry
• Skew Reduction H-Tree, Grid, Serpentine, Other
• Buffer Selection/Sizing Standard Cells, Modules
• Power Reduction
• Clock Gating
• Low Swing Drivers Receivers (Multiple Voltage
  Domains)

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Automation Issues

• Integration With Existing Design Flow
• How/Where to Integrate Clock Tree Synthesis Into
  Design Flow?
• Placement Routing of Buffers in Conjunction
  With Modules and Standard Cells.
• E.g. - How Do We Place Route Buffers For a
  Clock Domain Like Below? Which Blocks Are Sinks
  for Which Buffers?

Block A
Block B
Block C
Block D
Standard Cells
?
?
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Automation Issues (Cont.)

• Tools
• Commercial
• Already available
• - Less Control of How the Tree is Synthesized
• - Integration With Existing Design Flow is
  Questionable
• In House
• Allows for Control of Clock Distribution
  Synthesis Functionality
• Greater Flexibility to Integrate With Design
  Flow
• - Has to be Created Supported
• Verification
• SPICE Simulation, PathMill, RC Switch Level Sim.

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Implementation

• Current Design
• 2-Phase Non-Overlapping, Fully Synchronous, Full
  Scan
• Reset-able and Non-Reset-able MUX Scan FFs only
  (Q output only)
• Hand Designed Buffers and Gating Circuits
• Manually Placed Buffers, No Clock Tree

310 ?m
Fig. 2. Main Clock Gate and Driver
Fig. 1 Flip Flop Setup/Hold Time vs. Clock Edge
Time
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Implementation (Cont.)
Fig. 3 Simulink Representation of Clock Gate and
FF
Gating Buffer Design Data By Dejan Markovic
Fig. 4 Clock Gate and Driver Timing
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Future Work

• Characterize FFs to be used in Design (Dejan)
• Define System Level Implementation
• Start with Fully Synchronous Expand to Include
  Other Clocking Strategies
• Develop Automation Methodologies
• Choosing/Dividing Clock Sinks
• Choosing/Creating Appropriate Buffers Based on FF
  Data
• Placing Routing of Buffers
• Optimization Routines
• Flip-Flop Selection
• Voltage Domain Selection
• Insuring Compatibility With Design Flow