Degang Cheng, Eric Eisenbraun, Robert Geer, John Welch, and Alain Kaloyeros

1
Fabrication of Nanoscale Interconnect Performance
Test Structures

• Degang Cheng, Eric Eisenbraun, Robert Geer, John
  Welch, and Alain Kaloyeros
• School of Nanosciences and Materials
• UAlbany Institute for Materials
• University at Albany-SUNY

2
Molecular Electronics Task Organization
Synthesis Genetic Expression of protein-based
oligomeric systems
Fabrication Self-assembly of molecular wire
units into testable structures on a
conventional Si-based platform
Characterization Nanoscale SPM-based imaging and
electrical characterization of moletronic
structures
3
Program Goal

• Development of design and fabrication strategies
  to enable functionality and performance testing
  of molecular interconnects using conventional
  silicon CMOS technologies

4
Molecular Interconnect MaterialsSelf-Assembly
and Electronic Functionality
Napthyl-based functional group to enable
ballistic charge transport
Customized functional groups to enable directed
self-assembly on specific surfaces (e.g.
semiconductor-compatible noble metals and SiO2)
5
Functionality testingDirected self-assembly

• Silane-based groups on peptide backbone provide
  covalent attachment to SiO2 surfaces
• Specific groups to be employed trichlorosilane,
  trimethoxyalkyl silane
• Thiol-based groups provide covalent attachment to
  noble metal contacts
• Specific group to be employed thioacetyl

6
Functionality testingCharge Transport
Performance

• For first year proof-of-concept, benzyl groups
  employed (relative simplicity of fabrication)
• For second year charge transfer functionality
  testing, napthyl-based groups to be used
  (enhanced charge coupling attributes)

7
Charge Transport Measurements

• Nanoprobe test station (SPM platform)
• Conductance Slope of linear region of I-V
  response
• single strand and multistrand
• Contact resistance
• I-V slope vs. strand length
• Vthreshold in case of tunnel-coupling
• Junction resistance I-V slope vs. multi-strand
  length

Langlais et al. PRL 83, 2010 (1999)
8
Directed Self Assembly/ Electronic Functionality
Planar Test Structure Layout
Si3N4
SiO2
Al

• 19 test structures on one die
• All structures on one die share the same ground
  pad
• 1-4 µm exposed oxide widths

9
Directed Self Assembly/ Electronic Functionality
Planar Test Structure Layout
Si3N4
Al line to contact
Al (ground)
SiO2
Metal nanodot electrodes

• Electrodes spaced to be roughly equivalent to
  length of hexadecamer unit
• Allows testing of chain resistance, 4-point
  measurements
• Used for both self-assembly and electrical
  testing (resistance, current density)

10
Flow Chart for Molecular Interconnect Test
Structure Fabrication
Si3N4/ SiO2/Si Wafer
Al Etching (H3PO4HNO3HCAH2O16112)
Al Deposition (E-beam evaporation or sputtering)
Si3N4 Etching (RIE with SF6O2)
Lithography (Mask II for Al)
Lithography (Mask I for Si3N4)
Nanodot Preparation (FIB)
Nanodot Deposition (E-beam Evaporation)
Electron Beam Lithography (Mask III for Nanodots
)
Metal Etching (wet/dry)
Directed Self Assembly
Electrical Functionality Test
11
Second Generation Functionality Test Structures

• Inability to fabricate planar structures with
  molecular dimensions
• Potential of bundled, overlapping, or crossed
  wires, etc.
• Proposed solution--employ layer thickness as
  method to generate nanoscale functional surfaces

12
Directed Self Assembly/ Electronic Functionality
Molecular self-assembly on nanoscale lines
Electrode
Electrode
Electrode
Electrode
Ultra-thin (2-3nm) SiO2/Si3N4 single layer or
multilayer stacks- Micromachined by FIB or
lithography
13
Electronic Functionality Benchmarking Test
Structure

• Employ AFM- and FIB-based nanolithographic
  formation of fine lines (S.T.Yau, UAlbany) on
  patterned test structures
• Metal line formed from liquid suspension

Scribed nanoscale lines
Spin on metal-bearing solution
Cure, polish, and form contacts
14
Test Structure Directed Self-Assembly General
Points

• SiO2 and noble metals are functional surfaces
• Other metals and dielctrics (Al, Si3N4) are
  inert relative to molecular species
• Conventional semiconductor processes used for
  all steps
• Nanodots may be deposited by means of focused ion
  beam (FIB) or conventional lithography.
• Trenches generated by FIB, AFM, or EB lithography

15
Results to Date- Pt Nanostructure Fabrication

• Pt dots as small as 120 nm deposited on
  insulating substrates
• Good continuity over SiO2/Si3N4 transition regions

16
Current Status and Next Steps

• Mask designed and fabricated
• First structures fabricated with metal nanodots
• Self assembly feasibility underway
• Next Milestone12/31/01
• Fabrication of first-pass electrical test wafer
  structures
• Preliminary electrical testing results

17
Proposed Deliverables-2001

• By 9/1/01
• Report on viability of proposed process flow for
  fabrication of test structures
• Report on first-pass results of directed
  self-assembly concepts
• By 12/31/01
• Report on first-pass results of electrical
  testing of assembled structures.