Hierarchical Analysis of Power Distribution Network

1
Hierarchical Analysis of Power Distribution
Network
Advanced Tools, Motorola Inc., Austin, TX Dept.
Of ECE, University of Minnesota email
zhao_at_adttx.sps.mot.com

• Min Zhao, Rajendran V. Panda, Sachin S.
  Sapatnekar, Tim Edwards, Rajat Chaudhry, David
  Blaauw

2
Outline

• Introduction to power grid analysis
• Hierarchical analysis method
• Sparsification method
• Experimental results
• Conclusions

3
Power Grid Analysis Problem

• Parasitic resistance in power network and package
  cause supply voltage deviations on switching
  devices
• IR-drop
• Excessive supply variation affects
• performance
• signal integrity
• reliability

4
Typical Solution Approach

• Partition into nonlinear and linear networks

• Conservatism of ignoring effect of voltage on
  currents
• error is typically small in a well designed grid

5
Linear System Solution

• Form a differential equation from Modified Nodal
  Analysis approach Gx(t) Cx(t) b(t)
• G conductance matrix
• C capacitance matrix
• x(t) time varying vector of voltages
• b(t) time varying vector of independent current
  sources
• Reduce to a linear algebraic system by Backward
  Euler (GC/h)x(t) b(t)
  C/hx(t-h)
• Solve linear system YUJ
• Y is symmetric positive definite and sparse.
• Solution
• Conjugate gradient with preconditioning
  (Iterative)
• Cholesky factorization (Direct)

6
Outline

• Introduction
• Sparsification of macromodels
• Experimental results
• Conclusion

• Hierarchical analysis method
• Motivation
• Flow of hierarchical analysis
• Step 1 macromodeling
• Step 2 global solution
• Step 3 local solution
• Analysis of computation cost

7
Motivation

• In YUJ for entire chip
• Y is extremely large. (1 to 100 million nodes)
• Solving such a large dimension can cause problem
  in both memory and speed
• for example, 10 million node system may need more
  than 2GB memory and hours running time for the
  first time step
• New proposed hierarchical analysis method
• Partition the given network into subnetworks of
  manageable size.
• Model the interaction between subnetworks
  (partitions)
• Create macromodels for each partition
• In YUJ for entire chip, replace each partition
  with corresponding macromodel

8
Macromodels

• Each partition can be modeled as a multi-port
  linear element with transfer characteristics
• I A?V S
• V port voltages
• I currents flowing out of ports
• to nodes of other partition
• A port admittance matrix
• S current sources has the effect
  of moving
  current source of internal nodes to ports
• A macromodel
• Same linear relation between I and V as the
  partition
• Characterized as set (A,S)
• Macromodeling
• Derive macromodel from partitions linear system
  YUJ

9
Basic Idea

• Replace partitions with macromodels preserving
  the port I,V relation
• Density non-zero elements/matrix size

global
B1
B2
Original Linear system too large to be solved
Original design
10
Partitioning

• The power grid is partitioned into k partitions
• An example

global nodes
global grid
ports internal nodes
ports internal nodes
ports internal nodes
local grid
k partitions

• a is internal node links to nodes of the same
  partition
• b is port links to nodes of the other partition
  or global grid
• c is global node not within any local partition

11
Flow of the Hierarchical Analysis
12
Step1 Macromodeling

• Nodal equations of the partition

• U1 voltages at the internal nodes
• V voltages at the ports
• J1(J2) current source at internal nodes (ports)
• I currents through interface

• Rewrite the first set of equations
  U1G11-1(J1-G12V)
• Substitute into the second set of equations
• I(G22-G12TG11-1 G12)?V(G12TG11-1J1-J2)
• Macromodel (A,S) A G22-G12TG11-1 G12, S
  G12TG11-1J1-J2
• Most expensive computation G11-1G12
• one cholesky factorization
• m forward and backward substitution

13
Efficient Computation of Macromodel

• Cholesky factorization
• Plugged into macromodel (A,S)
• A G22-G12TG11-1 G12
• L21L21TL22L22T - L21 L11T (L11 L11T )-1
  L11L21
• L22L22T
• S G12TG11-1J1-J2
• L21L11T (L11T )-1 L11-1 J1 - J2
• L21L11-1 J1 - J2

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Step 2 Global Grid Solution

• Global grid global nodes and macromodels
• Stamped into modified nodal equations
• Gij conductance links between partition i and j
• I0(V0) current(voltage) of global nodes
• Vi port voltage of partition i
• (Ai,Si) macromodel of partition i
• A system of n0m1m2...mk linear equations
• n0 number of global nodes
• mi number of ports in partition i

15
Step 3 Local Grid Solution

• Obtain port voltages V from global solution
• Obtain voltages of internal nodes by
• U1G11-1(J1-G12V)
• which is from nodal equation of local grid
• Computation cost
• one forward and backward substitution

16
Computation Cost Based on Size

• Direct solution of linear systems
• the first run (cost1)
• one cholesky factorization about n 1.5 for
  sparse matrix
• the subsequent run (cost2)
• one forward and backward substitution near
  linear for sparse matrix
• Flat method cost1(N) N is the size of entire
  circuits
• Hierarchical analysis method
• ? all part(cost1(ni) mi?cost2(ni))
  cost1(n0m0m1...mk) ? all partcost2(ni)
• ni number of nodes in partition i n0 n1 n2
  ... n3 N
• mi number of ports in partition i
• The number of ports is crucial for the
  performance of hierarchical analysis method

17
Flat vs. Hierarchical Analysis Method

• Computation cost based on size
• Density important factor that influences
  solution speed
• Parallel execution
• Hierarchical analysis makes parallel execution of
  power grid analysis possible
• Provide flexibility to a design/analysis
  situation
• Iteratively analyze and fix only problematic
  partition

18
Outline

• Introduction
• Hierarchical analysis method
• Experimental results
• Conclusions

• Sparsification of macromodels
• Motivations
• Problem definition
• Problem formulation

19
Motivation for Sparsification

• Coefficient matrix A in the macromodel equation
  I A?V S
• Each element ai,j of A represents an equivalent
  conductance from port i to port j
• Typically, A is dense
• Some of these values may be numerically small so
  that neglecting them
• has little influence on the results
• but increases sparsity and speeds up global
  solution
• Objective for A
• zero out elements
• maintain positive definiteness and symmetry

20
Problem Definition

• Problem
• Given
• macromodel equation I A?V S
• The upper bound of V Bound, Bound?0
• The allowable error of ij ej, , j?1,m
• Find
• I A'?V S
• Maximize
• The number of aj,k in A, such that a j,k 0,
  j?k
• Subject to constraints
• ?I - I?? E, (error for current is limited)
• aj,k ak,j (A maintain matrix symmetry)

21
Problem Formulation

• Maximum negative error from rounding off
• ej,ka j,k?Bound, j?k
• Formulated as 0-1 multidimensional knapsack
  problem
• Maximize
• Subject to
• Xj,k is a Boolean value
• 1 element aj,k is rounded to zero
• 0 otherwise
• In the case of large dimension
• problem formulated as fractional knapsack problem
• solutions are sorted and snapped to 0 or 1

22
Outline

• Introduction
• Hierarchical analysis method
• Sparsification of macromodels
• Conclusions

• Experimental results

23
Experimental Results Hierarchical vs. Flat method

• Memory requirement reduced 10x-20x
• Chip-level analysis of very large designs (tens
  of million nodes) is possible
• Speed up
• Parallel run 10x-23x
• Serial run 2x - 5x

24
Hierarchical analysis - an example

• Routed grid of DSP chip
• 5 layers metal
• 30 million nodes

25
Performance of sparsification

• Each benchmark was tested at four levels of
  accuracy
• The hierarchical power analysis of chip-5 could
  not be solved with available computing resources
  without sparsification.

26
Conclusions

• A hierarchical power network analysis methodhas
  been presented.
• A novel matrix sparsification technique is
  included.
• Showed the performance of the above methodson
  chips.
• Conclusion
• The hierarchical analysis approach shows
  excellent promise as a viable alternative to the
  traditional nonhierarchical analysis method,
  capable of handling the increasing size of power
  grids in modern microprocessors