Device Interface Board for Wireless LAN Testing

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Device Interface Board for Wireless LAN Testing

• Team
• May 05-29
• Client
• ECpE Department

Faculty Advisor Dr. Weber Team Members Nathan
Gibbs EE Adnan Kapadia EE Daniel Holmes
EE/CprE Kyle Peters CprE
January 20, 2005
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Presentation Outline

• Project Overview
• Problem statement
• Operating environment
• Intended user(s) and use(s)
• Assumptions and limitations
• End product
• Project Activities
• Present accomplishments
• Future goals
• Approaches considered and one used
• Project definition activities
• Research activities
• Design
• Test and implementation
• Resources and Schedule
• Resource requirements
• Schedule
• Closure Materials

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Definitions

• DUT Device Under Test (Positive edge triggered
  D flip-flop)
• ESD wristband Electrostatic Discharge protective
  device
• Header Preamble bits for communication data
• Data packet Group of bits sent through a
  communication channel sequentially
• IG-XL Custom software for Teradyne Integra J750
• Kbps Kilo-bits per second
• Teradyne Integra J750 High speed digital tester
• TX/RX Transmitter/Reciever
• S/R Network Send and receive network
• PLL Phase-Locked Loop
• RF Radio Frequency

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Project Overview
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Project Overview

• Problem Statement
• Problem
• Wireless product testing is a requirement
• Currently, no way to interface Teradyne Integra
  J750 with a S/R network
• Test wireless products using the Teradyne Integra
  J750

• Solution
• Develop wireless interface to J750
• Develop test for DUT
• Solve latency issues and data transmission

?
Figure 1 Project Problem
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Project Overview

• Operating Environment
• 27C - 33C
• ESD wristbands
• IG-XL for Windows

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Project Overview

• Intended Users
• ECpE Faculty and Students
• Knowledge of Teradyne Integra J750
• Knowledge of RF components
• Intended Uses
• Functional test
• Signal test

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Project Overview

• Assumptions
• System
• Single channel communication
• Teradyne J750 will process despite delay
• User
• Manual for the Teradyne J750
• Knowledge of RF components
• Experience with an FPGA
• Understand the DUT operation

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Project Overview

• Limitations
• 27C - 33C
• Digital I/O only
• Usage of less common frequencies
• Wireless components limit data rate
• Teradyne cannot be moved
• RX/TX range approx. 100 feet

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Project Overview

• End Product and Other Deliverables
• S/R Network
• Failure or Success?
• Success
• Demonstration of test
• Manual to setup remote tests
• Failure
• Document describing findings
• Report to Teradyne

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Project Activities
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Project Activities

• Project Definition
• Initially wanted to test wireless components of
  device
• Research and advisor indicated task was too large
• Redefined project as proof-of-concept that J750
  can wirelessly test a device

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Project Activities

• Research Activities
• Feasibility of testing wireless components with
  J750
• Researched J750 setup and test creation
• Researched wireless system implementations
• Researched and evaluated components

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Project Activities
Design
Figure 2 System Design
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Project Activities

• Design Constraints
• Limited choice of frequency channels
• Lose precision from Teradyne Integra J750
• FPGA only at 25MHz
• TX/RX at 115kbps
• Distance between receivers and transmitters
  limited to 100 feet
• Budget limited to 150.00
• Team would like to have additional FPGAs for
  parallel to serial conversion

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Project Activities

• Present Accomplishments
• Ordered all components, received shift register
  and PLL
• Wrote test on J750 for device under test (Will
  modify for wireless test)
• Wrote FPGA code
• Tested and implemented shift registers

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Project Activities

• Future Required Activities
• Wirelessly test more devices using system
  developed
• Develop system to test wireless components
• Develop system for multiple users to test devices
  wirelessly

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Project Activities

• Approaches Considered
• System Design
• 2 FPGAs, 2 wireless transceivers
• 4 FPGAs, 2 wireless transmitters, 2 receivers
• 1 FPGAs, 2 wireless transmitters, 2 receivers,
  parallel to serial shift registers
• Advantages/Disadvantages
• Chose 3
• Only 1 FPGA available
• Simple, but effective implementation

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Project Activities

• Testing and Implementation
• No design modifications as of now
• Test each sub system individually
• Agenda
• Test the Shift Register
• Test the PLL and FPGA
• Test the S/R network
• Integrate subsystems into final setup and test
• Testing form

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Project Activities
Testing and Implementation
Figure 4 Testing form
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Resources and Schedule
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Resources and Schedule
Estimated Resources
Figure 5 -
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Resources and Schedule
Other Resources
Donated
84.90
Figure 6 - Resource Requirements
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Resources and Schedule
Project Final Costs
Figure 7 Project Costs with Labor
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Resources and Schedule
Figure 8 Major project tasks schedule
Figure 9 Project Deliverables
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Closing Material
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Closing Material

• Project Evaluation
• Inconclusive
• Commercialization
• Unlikely
• Cost
• Speed
• Immobile
• Possibilities
• RF companies
• Larger telecommunication companies

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Closing Material

• Recommendations for Additional Work
• Test other devices
• Test actual wireless network cards
• Improve upon FPGA speed
• Improve overall data rate
• Test actual RF links

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Closing Material

• Lessons Learned
• What went well?
• FPGA code worked
• Shift register performed as expected
• No issues with part selection or purchase
• Completed initial design
• What did not go well?
• Project definition
• Initial Teradyne J750 setup and test

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Closing Material

• Lessons Learned
• What technical knowledge was gained?
• Learned about RX/TX couples
• Learned about PLLs
• FPGA implementation
• Teradyne Integra J750 usage
• Parallel?Serial conversion

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Closing Material

• Lessons Learned
• What non-technical knowledge was gained?
• Communication skills
• Time management
• Negotiation skills

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Closing Material

• Lessons Learned
• What would have been done differently if the
  project had been done again?
• Define project earlier

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Closing Materials

• Potential Risks
• Teradyne Integra J750 signal latency
• Phase-Locked Loop fails to recover clock
• Encountered Risks
• Internships
• Receiver/Transmitter delivery delays

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Closing Materials

• Closing Summary
• Problem
• Solution
• Project still in development stage
• Cannot conclude on results

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Questions?
36
Thank You