IEEE 1149.4 Mixed-Signal Test Bus

1
IEEE 1149.4 Mixed-Signal Test Bus

• An overview of this new testability bus standard,
• along with a discussion of the architecture and
• how to use it.

2
IEEE 1149.4 Mixed-signal Test Bus Standard

• Development history
• Basic guidelines
• Test bus requirements
• Standard architecture
• Measurement example

3
Development History

• September 1991
• Informal meeting of 15 companies in San Jose, CA
• Draft of mission statement, objectives, request
  to IEEE
• October 1991
• ITC meeting attracted 30 companies
• Working Group authorized by Test Bus Steering
  Committee
• Working Group meetings
• Since October 1991
• Regular meetings 3 times per year at major test
  events

4
Mission Statement

• To define, document, and promote the use of a
• standard mixed-signal test bus that can be used
• at the device, sub-assembly, and system levels
• to improve the controllability and observability
  of
• mixed-signal designs and to support mixed-signal
• built-in test structures in order to reduce
• test development time and costs,
• and improve test quality.

5
Basic Guidelines

• Providing test bus facilities to meet the mission
  objectives
• Oriented toward industry design, test, and
  manufacturing
• Maintaining compatibility with 1149.1 test bus
  features
• Coordinating with
• IEEE 1149.1 and mainly the IEEE 1149.1B-1994
• International industry and academic experts

6
Basic Guidelines

• IEEE1149.4 does NOT seek to
• Solve all mixed-signal test problems
• Dictate mixed-signal test strategies
• IEEE1149.4 DOES intend to
• REDUCE the difficulty in mixed-signal testing
• FACILITATE design-for-test
• PROMOTE concurrent design test approaches

7
Mixed-Signal Printed Circuit Assembly
8
Common Defects on a mixed-signal PCA

• Opens
• Z
• Direct Connections

• Shorts
• D-D
• A-A
• D-A

• Missing Component
• Wrong Component

9
IEEE 1149.1 Boundary-Scan Architecture
Virtual Test Probe
TDI
TMS
CORE
CORE
TCK
TDO
CONNECTOR
PRINTED CIRCUIT ASSEMBLY
10
Simple, Extended and Differential Interconnects
11
Handling Analog Pins Pre-1149.4
Analog inputs
Analog section
Analog outputs
TDI Test Data In (1149.1) TMS Test Mode Select
(1149.1) TCK Test ClocK (1149.1) TDO Test Data
Out (1149.1) DBM Digital Boundary Module
(Boundary-Scan Cell)
DAC
ADC
Digital section
Digital inputs
Digital outputs
TDI
TMS
1149.1 Test Access Port
TDO
TCK
12
Handling Analog Pins with 1149.4
ABM
ABM
Analog inputs
TDI Test Data In (1149.1) TMS Test Mode Select
(1149.1) TCK Test ClocK (1149.1) TDO Test Data
Out (1149.1) DBM Digital Boundary Module
(Boundary-Scan Cell) ABM Analog Boundary
Module
Analog outputs
Analog section
ABM
ABM
DBM
DBM
Digital section
Digital outputs
Digital inputs
DBM
DBM
TDI
TMS
TDO
1149.1 Test Access Port
TCK
13
Structure of a basic 1149.4 chip (minimal config)
Analog Boundary Module (ABM)
Digital Boundary Module (DBM)
VH
VL
ANALOG I/O PINS
VG
DIGITAL
VH
I/O PINS
Internal Test Bus (AB1, AB2 )
VL
VG
Boundary Scan Path
AT1
Analog Test Access Port ATAP
AT2
TBIC (Test Bus Interface Circuit)
TDO
TDI
Digital Test Access Port (TAP ) as in IEEE1149.1
Digital Test Access Port (TAP) as in IEEE1149.1
Test Control Circuitry TAP Controller Instruction
register and decoder
TCK
TMS
14
Analog Boundary Module Input Pin
VTH
VH
VL
VG

• Input value can be sensed, digitised (against
  VTH), and captured in the register
• Current path into the core via AT1, AB1 and SB1
• Ability to disconnect the receiving core from the
  pin using SD and drive either a 1 or a 0 (SH or
  SL)
• ABMs can be implemented with actual switches or
  can be integral in the analog circuit.

-

SH
SL
SG
Analog function pin
SD
Core disconnect
SB2
SB1
AB1
Internal analog test bus
AB2
TBIC
AT1
AT2
ABM Switch Control
From TDI
To TDO
15
Analog Boundary Module Output Pin

• Dot 1 mode
• Logic 1/0 to output via SH/SL
• Digital signal input capture via comparison with
  VTH
• Compatible with 1149.1 Extest, Preload/Sample
• Analog mode each pin can
• source an analog current via AB1/SB1, or
• capture an analog voltage via SB2/AB2
• form a current return to VG (usually ground) via
  SG
• be disconnected from the core via SD

VTH
VH
VL
VG
Core
SH
SL
SG
Analog function pin
SD
Core disconnect
SB2
SB1
AB1
Internal analog test bus
AB2
TBIC
AT1
AT2
ABM Switch Control
From TDI
To TDO
16
Analog Output Cell
AB1
AB2

• VH and VL allow fixed 1 and 0 values (for
  EXTEST) using S1, S2, S3, S4
• ATn disconnected from ABn via S5, S8
• Noise suppression via S9, S10, Vclamp when ABn
  not in use

VH
Vclamp
S1
S2
S9
S10
VL
S3
S4
S5
S8
S7
S6
VTH
AT1
AT2
Provision for interconnect test
Bus connection and calibration
17
Analog Boundary-Scan






R
Z1
DR
DR
DR
DR
DR
DR
Z4
Z3
Z2
CORE
CORE
CORE






DR
DR
DR
DR
DR
DR
TDI
TDO
TAP
TAP
TAP
AT1
AT2
TMS
TCK
18
Test of R, Measurement V1






Z1
R
DR
DR
DR
DR
DR
DR
Z4
Z3
Z2
CORE
CORE
CORE






DR
DR
DR
DR
DR
DR
TDI
TDO
TAP
TAP
TAP
AT1
Constant Current
AT2
TMS
TCK
19
Test of R, Measurement V2






Z1
R
DR
DR
DR
DR
DR
DR
Z4
Z3
Z2
CORE
CORE
CORE






DR
DR
DR
DR
DR
DR
TDI
TDO
TAP
TAP
TAP
AT1
Constant Current
AT2
TMS
TCK
20
Test of R, Result

• R (V2 - V1) / I
• Results for three impedances (Z1, Z2, Z3) can be
  calculated and checked against correct values!
• This metrology was proven and presented at the
  1993 ITC by Ken Parker in a paper entitled
  Structure and Metrology for an Analog
  Testability Bus by Ken Parker, John McDermid,
  and Stig Oresjo of HP.

21
IEEE 1149.4 Types of Testing

• Interconnect Short, Open
• Parametric Testing Passive Element measurement
• Internal Testing DfT (Design for Test) , BIST
  (Built-In Self-Test)

22
For Further Information

• Officers
• Adam Osseiran, IEEE 1149.4 Working Group Chair
• Fluence Technology (Europe) osseiran_at_fluence.com
• Stephen Sunter, Vice Chair
• LogicVision, CANADA sunter_at_lvision.com
• Adam Cron, Editor (previous Chair)
• Synopsys, USA acron_at_synopsys.com
• Elbert Nhan, Secretary
• Johns Hopkins University, USA
  
• The IEEE 1149.4 Web page http//grouper.ieee.org
  /groups/1149/4/

23
To Learn more ....

• The IEEE Standard Document 0-7381-1755-2
  SH94761-NCD 59
• ITC97, P8.2 IEEE DTC, Fall 96, pp. 98-101
  (Cron, Viewlogic)
• ITC93, P15.2 (Parker et al, HP) ITC96, P15.1
  (Whetsel, TI) ITC96, P4.2 (Lofstrom, KLIC)
• K. Parker, Boundary-Scan Handbook Analog
  Digital, Kluwer, 1998 (2nd Edition). Chap. 7
• Perry, Fundamentals of Mixed-Signal Test, 1999,
  ltwww.soft-test.comgt
• A. Osseiran, Analog Mixed-Signal Boundary
  Scan a Guide to the 1149.4 Test Standard,
  Kluwer, 1999, ltwww.wkap.nlgt
• Next events DATE00 (Paris), VTS00 (Montreal),
  ITC00 (Atlantic City)