SEMI-SYNTHETIC

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SEMI-SYNTHETIC CIRCUIT GENERATION FOR
TESTING INCREMENTAL PLACE AND ROUTE TOOLS David
Grant Guy Lemieux University of British
Columbia Vancouver, BC
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Overview

• Introduction
• Circuit Generation Method 1 (FPL) doesnt work
  well
• Circuit Generation Method 2 (FPT) simple, works
  very well
• Circuit Scaling Extension
• Conclusions

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Introduction

• Problem
• (Free) Large digital circuits are rare
• FPGA CAD tools need large circuits
• Solution
• Generate random circuits
• But is random realistic?
• Goal
• Generate realistic random circuits (synthetic)
• Useful for testing place and route tools

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Introduction

• Past approaches
• Generate a complete synthetic circuit
• Tools ccirccgen, gnl
• New problem
• Real world development is iterative, incremental
• FPGA tools commonly used in incremental mode
• Need circuits with incremental changes

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Introduction

• Our Approach
• Start with a real circuit
• Generate a small synthetic change
• Result is a semi-synthetic circuit
• Four steps to generate a semi-synthetic circuit
• Identify
• Remove
• Generate
• Stitch (difficult?)

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Introduction

• Problem Blindly stitching a circuit can create
  combinational loops
• Cannot arbitrarily insert new latches to break
  loops

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Overview

• Introduction
• Circuit Generation Method 1 (FPL)
• Circuit Generation Method 2 (FPT)
• Circuit Scaling
• Conclusions

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Method 1 Introduction

• Four steps to generate a semi-synthetic circuit
• Identify sub-circuit (T-VPack)
• Remove sub-circuit
• Generate clone (ccircgnl, ccirccgen)
• Stitch
• Steps 1, 2, 3 are easy
• Stitching is difficult !!

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Method 1 Loop Graph, L

• Ideal Stitching
• Determine which outputs connect back to inputs
  through combinational logic
• If synthetic circuit generators could use L,we
  could stop here

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Graph L
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Method 1 Stitching

• Real Stitching takes 4 sub-steps
• Generate a dependence graph, D
• Calculated precisely from synthetic clone
  (subcircuit)
• Generate a permissible graph, P
• Calculated imprecisely from loop graph of host
  circuit
• Solve the monomorphism problem
• Find a monomorphism mapping D into P
• Stitch

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Method 1 a) Dependence Graph, D

• D is computed from synthetic clone
• Captures all combinational paths through clone

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Graph D
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Method 1 b) Permissible Graph, P

• P computed from L using heuristic
• Problem is NP-complete in general
• Start with loop graph L, consisting of only
  back-edges
• Add all forward edges to L, creating cycles ?
  call this P
• Find forward edge in cycle, remove it, repeat
  until P is cycle-free
• Remove all back-edges from P

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Graph P
Graph L
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Method 1 c) Monomorphism

• Monomorphism is like Isomorphism
• Except that number of edges need not be identical
• Find 11 vertex mapping of D to P
• D forward combinational paths in synthetic clone
• P permissible forward combinational paths

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(1,2) (2,1) (3,3) (4,4) (5,5)
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Graph D
Graph P
Mapping
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Method 1 d) Stitch

• Take the mapping solution and merge the clone
  into the hole left in the original circuit
• Mapping (2,1), (1,2), (3,3), (4,4), (5,5)

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Method 1 Discussion

• Good results for small cutout regions
• Unacceptably long run times for subcircuits gt 50
  I/Os
• Monomorphism solver is non-deterministic
• Preserved most key circuit characteristics
• Logic depth increases by factor 2-3x
• because method is unconstrained !
• Conclusion
• Stitching is not a trivial problem to solve (in a
  cycle-free way)

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Overview

• Introduction
• Circuit Generation Method 1 (FPL)
• Circuit Generation Method 2 (FPT)
• Circuit Scaling
• Conclusions

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Method 2 Introduction

• Four steps to generate a semi-synthetic circuit
• Identify sub-circuit (T-VPack)
• Remove sub-circuit
• Generate clone (perturber)
• Stitch
• The perturber does not profile and generate
• Instead, it perturbs the existing circuit
• Stitching is trivialized using this method

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Method 2 Perturbing a Circuit

• Perturber Algorithm
• Levelize the complete circuit
• Select a random edge in the sub-circuit (1
  source and 1 sink)
• Select a second edge in sub-circuit under
  certain constraints
• Swap the sinks
• Repeat

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Method 2 Perturbing a Circuit

• Perturber Algorithm (cont'd)
• Constraints guiding second edge selection
• Source and sink levels must match
• Source node cannot be sub-circuit input

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Method 2 Advantages of Perturber Algorithm

• Key circuit characteristics are exactly preserved
• Number of nodes and edges
• Fanout distribution
• Depth profile
• Strengths
• No combinational loops are created
• Because the levelization is preserved
• Very fast execution time
• Very simple approach

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Method 2 Initial Results

• Good results for small cutouts
• Less-than-impressive results for large cut-outs
• Cause
• Locality is lost during perturbation
• Independent buses are cross-connected
• Regular features of the circuit are lost
• Connections swapped across large regions of chip
• Need locality control !!

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Method 2 Ancestor Control

• Method to preserve locality
• Add additional edge selection constraint
• Source and sink levels must match
• Source node may not be sub-circuit input
• Both edges must share a common ancestor through
  combinational logic within a certain ancestor
  depth
• Stop at sub-circuit inputs and flops

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Method 2 Testing

• Know all the key circuit characteristics are
  preserved
• Focus comparisons on post-routing results
• Test 20 largest MCNC circuits
• Metrics channel width, delay, and wirelength
• goodness of result closeness to original MCNC
  result
• Test 1 Sanity test, full-circuit compare w/
  ccirccgen
• Test 2 Incremental semi-synthetic circuits

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Method 2 Sanity Check Results

• Channel Width of complete synthetic circuit

Overall cgen 20 error perturber 14
error
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Method 2 Sanity Check Results

• Delay of complete synthetic circuit

Overall cgen 7 error perturber 9 error
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Method 2 Sanity Check Results

• Wirelength for a complete synthetic circuit

Overall cgen 24 error perturber 17
error
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Method 2 Testing

• Test 2 Incremental Circuit Results
• Generate semi-synthetic incremental circuit
• Change only 5, 10, 20 of real circuit
• No previous work to compare against

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Method 2 Incremental Results

• Channel Width for various cutouts

Overall 5 2.6 error 10 3.2
error 20 6.7 error
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Method 2 Incremental Results

• Delay for various cutouts

Overall 5 5.5 error 10 6.4
error 20 8.7 error
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Method 2 Incremental Results

• Wirelength for various cutouts

Overall 5 1.4 error 10 2.2
error 20 3.9 error
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Method 2 Discussion

• Sanity Check
• Complete circuit result error lt ccirccgen
  error(error reduced by 1/3)
• Incremental Circuits
• Close to original (1-6) using 5, 10 cutouts
• More deviation (4-9) at 20 cutout

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Overview

• Introduction
• Circuit Generation Method 1 (FPL)
• Circuit Generation Method 2 (FPT)
• Circuit Scaling
• Conclusions

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Circuit Scaling

• Scaling
• Reduce the size of the cutout region
• so the tools have to fill in holes
• Increase the size of the cutout region
• so the tools have to make room for larger circuit
• Approach
• Scale a circuit (mutator), then perturb it

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Circuit Scaling

• Reduction
• Shotgun approach delete nodes at random
• Sometimes need to delete chains of logic
• Enlargement
• Duplicate circuit in parallel
• Multiplex inputs and outputs with LUTs
• Doubles (, triples, etc) circuit
• Enlargementreduction to achieve arbitrary scaling

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Circuit Scaling Results

• Test 5, 10, 20 cutout
• Scale cutout size to 50, 75, 200, 400
  original
• No unexpected changes in post-routing
  characteristics from MCNC original
• Some expected changes
• Eg, wirelength increased as cutout size enlarged

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Conclusions

• Have shown how to create a semi-synthetic circuit
• Method 2 is a superior method over past
  approaches
• Runtime, simplicity
• Preservation of key circuit properties
• Preserve them first, find ways to alter them
  later
• Quality of result
• Scaling is able to change the circuit size
  without changing the post-routing characteristics
  in unexpected ways

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Future Work

• Critical Path
• Lengthen the critical path to force the tools to
  shuffle nodes along the critical path
• Mutate other circuit properties?
• Node depth profile
• Fanout distribution
• Fanin distribution
• Wire lengths

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It's Over

• Questions?
• Comments?
• Concerns?

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