Submission of Pixel ROC in DSM

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Submission of Pixel ROC in DSM

• After 10 month of design time ( not counting
  approx. 4 month of CAD preparation)
• Submission of new pixel ROC in IBM 0.25m
  technology finally happened !!
• Many thanks to
• H-Ch. Kaestli, W. Erdmann, G. Dietrich, B.
  Meier, M. Barbero, Ch. Hoermann, R.H.
• Wafers expected back in approx. 7-8 weeks.
• PCB test board for new chip has been sent to
  manufacturer.

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Recticle of IBM-PSI46

• Recticle size 17400m x 21200m

ROC_C_TP

• 4 versions of ROC (A,B,C, C_TP)
• - various SEU power decoupling scenarios
• - Testpoint (TP) version of ROC_C
• SEU teststructures (2)
• HDI-LVDS-driver chip (2x)
• Kaptoncable-driver chip (3x)
• I2C-teststructures
• Analog readout chain teststructures
• Pixel teststructures (various)
• DAC,regulator,etc teststructures
• Bumpbonding alignement marks
• 62 recticles / 8 wafer

ROC_C
ROC_A
ROC_B
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token out
HDI LVDS Driver Chip

• Chip size 2mm x 1mm
• Bandgap reference () voltage regulator
• Distributes 5 LVDS signals into 4 ports
• TBM replacement for first module tests
• Chip needs decoupling capacitors (2)
• Drives lines as capacitive loads

LVDS outputs
LVDS outputs
Reset (CMOS)
Reset (CMOS)
LVDS outputs
LVDS outputs
token out
() we thank group of P. Jarron , CERN
LVDS - inputs
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Kapton Cable Driver Chip
LVDS input

• Chip size 3 mm x 1mm
• Bandgap reference () voltage regulator
• Drives 5 LVDS signals into transmission lines
• Back termination for Z 25 45 W
• Termination adjustment by 2 external resistors
• 4-bit setting (hex) of 0-3 nsec delay
• Chip needs decoupling capacitors (5x)
• Power dissipation 3 5 mA _at_ 2.5V

LVDS output
LVDS input
LVDS output
LVDS input
LVDS output
LVDS input
LVDS output
LVDS output
LVDS input
hex delay 0-3ns (wirebondable)
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7900mm
DSM Pixel ROC
IBM_PSI46

• Chip considerable modified compared to DMILL
  version
• - should have uniform address levels
• External operation is same
• Less pads (35)
• - I2C clock only with 3 small reserve pads !
• less power voltages (2)
• less current ( 70mA)
• smaller in height ( 1mm)
• new features ( temp. sensor )

9800mm
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SPICE simulation of complete chip

• extensive verifications simulations done ! !
• heavy CPU usage ! ! !

Analog out signal of ROC
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Data losses of pixel ROC

• Original ROC design (TDR) was done for high
  lumi operation of 7cm layer!
• Use 0.25m ROC translation to optimize for new
  pixel size and 4cm radius !!

Data losses _at_ r4cm L1034 DMILL ROC DM_PSI43 150m x 150m pixel 0.25mm ROC IBM_PSI46 100m x 150m pixel
Timestamp ( buffers) 3.1 (8) 0.17 (12)
Data Buffers ( buffers) 0.1 (24) 0.15 (32)
Column Drain load cycle 3 0
Column Drain 3rd hit capability 1.4 0.25
Pixel overwrite 0.3 0.21
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Parameters of new DSM Pixel Read Out Chip

• Chipname IBM_PSI46
• CMOS technology IBM 0.25mm, bulk, 5
  Metals (old DMILL_PSI43 0.8m BiCMOS, SOI, 2 Met
  )
• Size of final ROC layout 7900 m x 9800
  m (old DMILL_PSI43 7950m x 10800m )
• 52 x 80 pixel 4160 pixel (old
  DMILL_PSI43 52x53 pixel 2756 pixel )
• Pixel size (rj x z) 100 mm x 150 mm (old
  DMILL_PSI43 150m x 150m )
• Number of transistors 1280 K (old
  DMILL_PSI43 430 K )
• Number of supply pads 35 pads ( 175m
  pitch ) (old DMILL_PSI43 42 pads of 150m pitch
  )
• Number of external capacitors 2 (old
  DMILL_PSI43 6 )
• Number of supply voltages 2
  (2.5V,1.75V) (old DMILL_PSI43 4 (5V, 3.5V,
  3V, 2.5V) )
• Total supply current estim. 70 mA (old
  DMILL_PSI43 160 mA )

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Pads of DSM ROC
Pad-No Signal Pad-size a i2c_clk small b i2c
_clk- small c i2c_clk_sel small 1 GND_CAP big
2 GND big 3 token_in big 4 token_in- big 5 r
eset big 6 aout big 7 aout- big 8 GND big
9 trig_out big 10 trig_out- big 11 CAP_VD big
12 cal_trig_res big 13 cal_trig_res- big 14 c
lk big 15 clk- big 16 VA big 17 VA big 18 V
C big 19 GND big 20 GND big 21 CAP_DAC big 22
i2c_a3 big 23 i2c_a2 big 24 i2c_a1 big 25 i2c_
a0 big 26 i2c_dat big 27 i2c_dat- big 28 token
_out big 29 token_out- big 30 CAP_dig_reg big
31 VD big 32 VD big 33 GND big 34 GND big 35
GND_CAP big
IBM_PSI46
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Module dimensions for DSM ROC
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Layout progress of HDI for new DSM Pixel ROC

• new HDI in the works ? expect submission
  Aug.03
• 3 layers design ( 7m Cu thick with 50 grid
  3-4m effective)
• try to design for good yield !
• improve mounting and bonding capability (
  lesson of 1st iteration)

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Construction of DMILL modules
History of modules Module 00 PCB module, HDI ,
16 chips , dummy silicon sensor Module 0
Si-baseplate, HDI, 16 chips, silicon pixel
sensor (defect components) Module 1
Si-baseplate, HDI, 16 chips, silicon pixel
sensor (poor quality comp.) Module 2
Si-baseplate, HDI, 16 chips, silicon pixel
sensor (poor quality comp.) Module 3
Si-baseplate, HDI, 16 chips, silicon pixel
sensor (med. quality comp.) Module 4
Si-baseplate, HDI, 16 chips, silicon pixel
sensor (best quality comp)

• Fabrication of Module 1-4 with improved
  procedures and jigs
• HDI cables done with new module handles
• Chips bumpbonded and tested with 200g per chip
  pull test!
• Chip positions measured after bumpbonding (
  deviation lt 1-2m )

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Module handles
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Module handle on vacuum table
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Module handles on vacuum table
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HDI is placed held by vacuum to module
handle
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TBM replacement, termination chips power cable
attached bonded
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Kapton signal cable attached bonded
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Details of TBM replacement chips (LVDS drivers)
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Termination chips
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Storage box for module-handles
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Silicon baseplate with decoupling capacitors
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Silicon sensor bumbonded to 16 chips
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Final assembled pixel module