Random Number Generator

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Random Number Generator

• Dimtriy Solmonov W1-1
• David Levitt W1-2
• Jesse Guss W1-3
• Sirisha Pillalamarri W1-4
• Matt Russo W1-5
• Design Manager Thiago Hersan

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Agenda

• Overview of project
• Status
• Decisions
• Signal flow on Floor Plan
• Critical Path
• Schematic Screen Shots

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A Quick Review

• Applications encryption, gambling, personal
  computers, etc.
• Goal faster random number generation than
  current software.
• Algorithm
• 1028 bit seed fed into RAM
• Feedback loop repeats 256 times to hash the seed
  and produce a pseudorandom number.
• Two stage, five clocks per stage pipeline.

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Status

• Last Time
• C implementation
• Architecture
• Behavioral Verilog Datapath design
• Finished Simulation
• Gate-Level Design
• Preliminary Floorplan
• In Process
• Schematic (mostly done)
• Layout (gates)
• Unfinished
• Extraction, LVS, post-layout simulation

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Design Decisions

• No sense amps

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Layout Decisions

• Lithography resolution enhancement
• As transistors become small
• More regular layout, layout rules
• Metal Direction

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What does it mean?

• Increasing problems with printability
• Optical wavelengths are smaller than critical
  distances
• Introduction of Resolution Enhancement Techniques
  to aid lithography
• Optical Proximity Correction modifies layout to
  improve printing

sources 18-322 Lecture 27, Fall 2003
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Regularity-Based Restrictive Design Rules

• Having layout that adheres to more strict design
  rules are becoming necessary for modern printing
  techniques
• Want to keep each layer as simple as possible
• Current research at CMU proposes
  regularity-driven layout
• Layout Optimization at the Pinnacle of Optical
  Lithography, L. Liebmann et al. SPIE 2003.
• Design Methodology for IC Manufacturability
  Based on Regular Logic-Bricks, V. Kheterpal et
  al. DAC, 2005.

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How does it affect us?

• Restrictive design rules include
• Single orientation and fixed pitch for critical
  lines (poly, M1, M2)
• Metal Layers
• Vertical Poly, M1, M3
• Horizontal M2, M4
• Contacts and vias are also on a grid
• Work with Thiago to define rules
• Implications
• Cons
• Probably bigger area (lower density)
• Need for extra metal layer
• Pros The way of the future

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typedef unsigned int u4 / unsigned four bytes,
32 bits / define ALPHA (8) define SIZE
(1ltltALPHA) define ind(x) ((x)(SIZE-1))
define barrel(a) (((a)ltlt19)((a)gtgt13)) /
beta32,shift19 / static void ibaa(m,r,aa,bb)
u4 m / Memory array of SIZE ALPHA-bit terms
/ u4 r / Results the sequence, same size as
m / u4 aa / Accumulator a single value /
u4 bb / the previous result / register
u4 a,b,x,y,i a aa b bb for (i0
iltSIZE i) x mi a barrel(a)
mind(i(SIZE/2)) / set a / mi y
mind(x) a b / set m / ri b
mind(ygtgtALPHA) x / set r / bb b
aa a
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Signal Flow on Floor Plan
725 um²
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Critical Path

• FSM
• Runs at .55 n
• Adder
• Runs at .6 n (critical 13 bits)
• SRAM
• lt .5 n

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SRAM Schematic
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Adder Schematics 3-Bit Generate
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Adder Schematics 3 Bit Propagate
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Adder Schematics 3 Bit CS Adder
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Quick Bibliography

• Techniques for Fast CMOS-based Conditional Sum
  Adders
• Hands Lindkvist and Per Andersson
• High Efficient 3-input XOR for Low-Voltage
  Low-Power High-Speed Applications
• Kuo-Hsing Cheng and Ven-Chieh Hsieh
• Carry-Look-Ahead and Ling Adders
• Stanford University
• L. W. Liebmann (slides)
• IBM

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Thanks! Any Questions?