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Advance encryption Standard VHDL implementation

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Design, simulation and implementation of symmetric encryption system. 10/4/09 ... Difference between synthesis softwares. Knowledge of synthesis algorithms. ... – PowerPoint PPT presentation

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Title: Advance encryption Standard VHDL implementation


1
Advance encryption StandardVHDL implementation
  • Florida International University
  • Department of Electrical and Computer Engineering
  • Fall 2003
  • By
  • Wilson Luengas
  • Richard Zavaleta
  • Luis Gonzalez

2
Objective
  • Design, simulation and implementation of
    symmetric encryption system.

3
Importance of Data and Network Security
  • Interception, modification or destruction of
    sensitive data may cause great personal and
    financial distress.
  • Popularity of online transactions and digital
    storage.

4
Data and network security limitations
  • There is no 100 secured networks.
  • Attackers may be hackers or disgruntled
    employees.
  • Breach of security may be due to negligence of
    employees or absence of security policy.
  • New viruses are created all the time.

5
Advance Encryption Standard (AES)
  • NIST chose the Rijndael algorithm as its AES
    standard in 2001 1.
  • No known security attacks.
  • It can be implemented in 8-bits, 64-bits
    platforms, and DSP.
  • Low RAM and ROM requirement.

6
AES Parameters
7
AES 128-bits Encryption Structure
8
Add Round Key Transformation
Example
9
Byte Substitution Transformation
S-box Matrix
State
Byte substitution Matrix
10
Shift Row Transformation
a0
ad
c9
95
a0
ad
c9
95
1b
7e
62
d5
1b
7e
62
d5
fb
85
bd
2d
2d
fb
85
bd
19
76
ce
2c
19
76
ce
2c
Shift Row Matrix
State
11
Mix Column Transformation
12
Tools Equipment
  •         Microsoft Visual C 6.0
  •         CPLD Proto Board Cypress P/N CY4000
  • o       CY39100V208B-82NTC
  • o       Cy37256VP160-66AC
  •         Mentor Graphic LeonardoSpectrum 2002,
    synthesis software.
  •         Modelsim 5.6f, simulation software.
  •         Cypress Lab CD-ROM.
  • o       Warp 6.3
  • o       IRS Release 3.0.7

13
Simulation Results
14
Simulation Results (Cont)
15
File Encryption
16
File Data Transfer
17
FPGA Devices
CY39100V208B-83NTC
CY37256VP160-66AC
18
Design Constrains
  • Number of pins
  • Number of Logic Units
  • Number of Macrocells

19
CY39100V Fitting
20
Design Splitting
21
Design Optimization


22
Design Splitting (Cont)
23
Scaled Down Design
24
Chip Resource Summary
25
Future Work
26
Conclusions
  • Knowledge of devices resources.
  • Difference between simulation software and
    synthesis software.
  • Difference between synthesis softwares.
  • Knowledge of synthesis algorithms.
  • Divide and conquer approach.
  • Use full development kit.

27
References
  • National Institute of Standards and Technology.
    Specifications for the Advanced Encryption
    Standard (AES), http//csrc.nist.gov/publications/
    fips/fips97/fips-197.pdf, (2001).
  • J. J. Buchhloz, Advanced Encryption Standard,
    http//buchholz.hs-bremen.de, Dec. 2001.
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