Title: ECE3120: Chapter 8 Timer Functions OC Function
1ECE3120 Chapter 8- Timer FunctionsOC Function
- Dr. Xubin He
- http//iweb.tntech.edu/hexb
- Email hexb_at_tntech.edu
- Tel 931-3723462, Brown Hall 319
2Output Compare Function
- The HCS12 has eight output compare functions.
- Each output compare channel consists of
- A 16-bit comparator
- A 16-bit compare register TCx (also used as inout
capture register) - An output action pin (PTx, can be pulled high,
pulled low, or toggled) - An interrupt request circuit
- A forced-compare function (CFOCx)
- Control logic
3Operation of the Output-Compare Function
- One of the applications of the output-compare
function is to trigger an action at a specific
time in the future. - To use an output-compare function, the user
- Makes a copy of the current contents of the TCNT
register - Adds to this copy a value equal to the desired
delay - Stores the sum into an output-compare register
(TCx, x 0..7)
- The actions that can be activated on an output
compare pin include - Pull up to high
- Pull down to low
- Toggle
4Operation of the Output-Compare Function
- The action is determined by the Timer Control
Register 1 2 (TCTL1 TCTL2) - A successful compare will set the corresponding
flag bit in the TFLG1 register. - An interrupt may be optionally requested if the
associated interrupt enable bit in the TIE
register is set.
5Operation of the Output-Compare Function
- Example 8.4 Generate an active high 1 KHz digital
waveform with 30 percent duty cycle from the PT0
pin. Use the polling method to check the success
of the output compare operation. The frequency of
the E clock is 24 MHz.
Solution An active high 1 KHz waveform with 30
percent duty cycle is shown in Figure 8.19. The
logic flow of this problem is illustrated in
Figure 8.20. Setting the prescaler to the TCNT to
8, then the period of the clock signal to the
TCNT will be 1/3 µs. The numbers of clock cycles
that the signal is high and low are 900 and 2100,
respectively.
6Generating 1 KHz Digital Waveform
include "c\miniide\hcs12.inc" hi_time equ
900 lo_time equ 2100 org 1500 movb
90,TSCR1 enable TCNT with fast
timer flag clear movb 03,TSCR2
disable TCNT interrupt, set prescaler to 8 bset
TIOS,OC0 enable OC0 movb
03,TCTL2 select pull high as pin
action ldd TCNT start an OC0
operation with 700 us as delay repeat addd
lo_time " std TC0
" low brclr TFLG1,C0F,low
wait until OC0 pin go high movb 02,TCTL2
select pull low as pin action ldd TC0
start an OC operation with 300 us
as delay addd hi_time " std
TC0 " high brclr
TFLG1,C0F,high wait until OC0 pin go
low movb 03,TCTL2 select pull high
as pin action ldd TC0 bra repeat end
7- Example 8.5 Write a function to generate a time
delay which is a multiple of 1 ms. Assume that
the E clock frequency is 24 MHz. The number of
milliseconds is passed in Y.
- Solution One method to create 1 ms delay is as
follows - Set the prescaler to TCNT to 64
- Perform the number of output-compare operations
(given in Y) with each operation creating a 1-ms
time delay. - The number to be added to the copy of TCNT is
375. (375 ?? 64 ? 24000000 1 ms)
delayby1ms pshd movb 90,TSCR1 enable TCNT
fast flags clear movb 06,TSCR2 configure
prescaler to 64 bset TIOS,OC0 enable OC0 ldd
TCNT again0 addd 375 start an output-compare
operation std TC0 with 1 ms time
delay wait_lp0 brclr TFLG1,OC0,wait_lp0 ldd TC0
dbne y,again0 puld rts
8- Example 8.6 Use an input-capture and an
output-compare functions to measure the frequency
of the signal connected to the PT0 pin.
- Example 8.6 Use an input-capture and an
output-compare functions to measure the frequency
of the signal connected to the PT0 pin. - Solution To measure the frequency, we will
- Use one of the output-compare function to create
a one-second time base. - Keep track of the number of rising (or falling)
edges that arrived at the PT0 pin within one
second.
include "c\MiniIDE\hcs12.inc" CR equ 0D LF eq
u 0A org 1000 oc_cnt rmb 1 frequency rmb 2 or
g 1500 movb 90,TSCR1 enable TCNT and fast
timer flags clear movb 02,TSCR2 set prescale
factor to 4 movb 02,TIOS enable OC1 and
IC0 movb 100,oc_cnt prepare to perform 100
OC1 operation, each creates 10 ms delay and
total 1 second movw 0,frequency initialize
frequency count to 0 movb 01,TCTL4 prepare
to capture the rising edges of PT0 movb C0F,TFLG
1 clear the C0F flag bset TIE,IC0 enable
IC0 interrupt cli "
9 ldd TCNT start an OC1 operation with 10
ms delay continue addd 60000
" std TC1 " w_lp brclr TFLG1,C1F,w_lp
wait for 10 ms ldd TC1 dec
oc_cnt bne continue ldd frequency pshd ldd m
sg jsr printf,PCR leas 2,sp swi msg db CR,LF,
"The frequency is d",CR,LF,0 TC0_isr ldd TC0
clear C0F flag ldx frequency increment
frequency count by 1 inx
" stx frequency rti org 3E6E
set up interrupt vector number fdb TC0_isr
for TC0 end
10Making Sound Using the Output-Compare Function
- A sound can be generated by creating a digital
waveform with appropriate frequency and using it
to drive a speaker or a buzzer. - The circuit connection for a buzzer is shown in
Figure 8.21. - The simplest song is a two-tone siren.
11Algorithm for Generating a Siren
- Step 1
- Enable an output compare channel to drive the
buzzer (or speaker). - Step 2
- Start an output compare operation with a delay
count equal to half the period of the siren and
enable the OC interrupt. - Step 3
- Wait for the duration of the siren tone (say half
a second). During the waiting period, interrupts
will be requested many times by the output
compare function. The interrupt service routine
simply restart the output compare operation. - Step 4
- At the end of the siren tone duration, choose a
different delay count for the output compare
operation so that the siren sound may have a
different frequency. - Step 5
- Wait for the same duration as in Step 3. During
this period, many interrupts will be requested by
the output compare operation. - Step 6
- Go to Step 2.
12- Example 8.7 Write a program to generate a
two-tone siren that oscillates between 300 Hz and
1200 Hz. - Solution
- Set the prescaler to TCNT to 18.
- The delay count for the low frequency tone is
(24000000 ? 8) ? 300 ? 2 5000. - The delay count for the high frequency tone is
(24000000 ? 8) ? 1200 ? 2 1250.
include "c\miniide\hcs12.inc" hi_freq equ
1250 delay count for 1200 Hz (with
18 prescaler) lo_freq equ 5000
delay count for 300 Hz (with 18
prescaler) toggle equ 04 value
to toggle the TC5 pin org 1000 delay ds.w
1 store the delay for
output-compare operation org 1500 lds
1500 movw oc5_isr,UserTimerCh5 initialize
the interrupt vector entry movb 90,TSCR1
enable TCNT, fast timer flag clear movb
03,TSCR2 set main timer prescaler to 8
13 bset TIOS,OC5 enable OC5 movb
toggle,TCTL1 select toggle for OC5 pin
action movw hi_freq,delay use high
frequency delay count first ldd TCNT
start the low frequency sound addd delay
" std TC5
" bset TIE,OC5 enable OC5
interrupt cli " forever
ldy 5 wait for half a
second jsr delayby100ms " movw
lo_freq,delay switch to low frequency delay
count ldy 5 jsr delayby100ms movw
hi_freq,delay switch to high frequency delay
count bra forever oc5_isr ldd TC5 addd
delay std TC5 rti include c\miniide\delay.a
sm end
14Playing Songs Using the OC Function
- Place the frequencies and durations of all notes
in a table. - For every note, use the output-compare function
to generate the digital waveform with the
specified frequency and duration. - The next example plays the US national anthem.
15include "c\miniide\hcs12.inc" G3 equ 7653
delay count to generate G3 note (with 18
prescaler) B3 equ 6074 delay count to generate
B3 note (with 18 prescaler) C4 equ 5733 delay
count to generate C4 note (with 18
prescaler) C4S equ 5412 delay count to generate
C4S (sharp) note D4 equ 5108 delay count to
generate D4 note (with 18 prescaler) E4
equ 4551 delay count to generate E4 note (with
18 prescaler) F4 equ 4295 delay count to
generate F4 note (with 18 prescaler) F4S equ 4054
delay count to generate F4S note (with 18
prescaler) G4 equ 3827 delay count to generate
G4 note (with 18 prescaler) A4 equ 3409 delay
count to generate A4 note (with 18
prescaler) B4F equ 3218 delay count to
generate B4F note (with 18 prescaler) B4 equ 3037
delay count to generate B4 note (with 18
prescaler) C5 equ 2867 delay count to generate
C5 note (with 18 prescaler) D5 equ 2554 delay
count to generate D5 note (with 18 prescaler) E5
equ 2275 delay count to generate E5 note (with
18 prescaler) F5 equ 2148 delay count to
generate F5 note (with 18 prescaler) notes equ 10
1 toggle equ 04 value to
toggle the TC5 pin
16 org 1000 delay ds.w 1
store the delay for output-compare
operation rep_cnt ds.b 1 repeat the song this
many times ip ds.b 1 remaining notes to be
played org 1500 lds 1500 establish
the SRAM vector address for OC5 movw oc5_isr,Use
rTimerCh5 movb 90,TSCR1 enable TCNT, fast
timer flag clear movb 03,TSCR2 set main
timer prescaler to 8 bset TIOS,OC5 enable
OC5 movb toggle,tctl1 select toggle for
OC5 pin action ldx score use as a pointer to
score table ldy duration points to duration
table movb 1,rep_cnt play the song
twice movb notes,ip movw 2,x,delay start
with zeroth note ldd TCNT play the first
note addd delay " std TC5 " bset TIE,C5I
enable OC5 interrupt cli
"
17forever pshy save duration table pointer in
stack ldy 0,y get the duration of the
current note jsr delayby10ms
" puly get the duration pointer from
stack iny move the duration pointer iny
" ldd 2,x get the next note, move
pointer std delay " dec ip bne forever dec r
ep_cnt beq done if not finish playing,
re-establish ldx score pointers and loop
count ldy duration " movb notes,ip
" movw 0,x,delay get the first note delay
count ldd TCNT play the first
note addd delay " std TC5 bra
forever done swi
18oc5_isr ldd TC5 addd delay std
TC5 rti
The following subroutine creates a time delay
which is equal to Y times 10 ms. The timer
prescaler is 18.
delayby10ms bset TIOS,OC0 enable
OC0 ldd TCNT again1 addd 30000 start an
output-compare operation std TC0 with 10 ms
time delay wait_lp1 brclr TFLG1,C0F,wait_lp1 ldd
TC0 dbne y,again1 bclr TIOS,OC0
disable OC0 rts
19score dw D4,B3,G3,B3,D4,G4,B4,A4,G4,B3,C4S dw D4,
D4,D4,B4,A4,G4,F4S,E4,F4S,G4,G4,D4,B3,G3 dw D4,B3
,G3,B3,D4,G4,B4,A4,G4,B3,C4S,D4,D4,D4 dw B4,A4,G4
,F4S,E4,F4S,G4,G4,D4,B3,G3,B4,B4 dw B4,C5,D5,D5,C
5,B4,A4,B4,C5,C5,C5,B4,A4,G4 dw F4S,E4,F4S,G4,B3,
C4S,D4,D4,G4,G4,G4,F4S dw E4,E4,E4,A4,C5,B4,A4,G4
,G4,F4S,D4,D4 dw G4,A4,B4,C5,D5,G4,A4,B4,C5,A4,G4
Each of
the following entries multiplied by 10 ms gives
the duration of a note.
duration dw 30,10,40,40,40,80,30,10,4
0,40,40 dw 80,20,20,60,20,40,80,20,20,40,40,40,40
,40 dw 30,10,40,40,40,80,30,10,40,40,40,80,20,20
dw 60,20,40,80,20,20,40,40,40,40,40,20,20 dw 40,
40,40,80,20,20,40,40,40,80,40,60,20,40 dw 80,20,2
0,40,40,40,80,40,40,40,20,20 dw 40,40,40,40,20,20
,20,20,40,40,20,20 dw 60,20,20,20,80,20,20,60,20,
40,80 end
20Using OC7 to Control Multiple OC Functions
- OC7 can control up to eight channels of OC
functions. - The register OC7M specifies which OC channels are
controlled by OC7. - The register OC7D specifies the value that any
PTx pin to assume when the OC7 operation
succeeds. - For OC0 to OC6, when the OC7Mn (n 0,,6) bit is
set, a successful OC7 compare overrides a
successful OC0OC6 compare pin action during the
same cycle.
21- Example 8.9 What value should be written into
OC7M and OC7D if one wants pins PT2, PT3, and PT4
to assume the values of 1, 0, and 1, respectively
when OC7 compare succeeds?
- Solution
- 4, 3, and 2 of OC7M must be set to 1, and bits 4,
3, 2, of OC7D should be set to 1, 0, and 1,
respectively. - The following instruction sequence will achieve
the desired effect - movb 1C,OC7M
- movb 14,OC7D
22Forced Output-Compare (1 of 2)
- There are applications in which the user wants an
output compare in action to occur immediately
instead of waiting for a match between the TCNT
and the proper output compare register. - This situation arises in the spark plug timing
control and some automotive engine control
applications. - To force an output compare operation, write ones
to the corresponding bit in the CFORC register. - At the next timer count after the write to the
CFORC register, the forced channels will trigger
their programmed pin actions to occur.
23Example 8.12 Suppose that the contents of the
TCTL1 and TCTL2 registers are D6 and 6E,
respectively. The contents of the TFLG1 are 00.
What would occur on pins PT7 to PT0 on the next
clock cycle if the value 7F is written into the
CFORC register?
- Solution
- The TCTL1 and TCTL2 configure the output-compare
actions as shown in Table8.2. - The TFLG1 register indicates that none of the
started output-compare operations have succeeded
yet. - The actions indicated in Table 8.2 will be forced
to occur immediately.
24Next
- PAI and PWM functions
- Read Ch. 8.7-8.11