Dependable Testing of Compactor MISR: an Imperceptible Problem

1
Dependable Testing of Compactor MISR an
Imperceptible Problem?

• Andrzej Hlawiczka, Michal Kopec
• Institute of Electronics, Silesian University of
  Technology, Poland

2
Outline

• Motivation When does the information that
  confirms the compactor correctness need to be
  given?
• Traditional approaches to testing MISRs
• disadvantages
• MISR-NOT compactor and a new idea of testing
• Properties of a MISR-NOT compactor
• Determining the test length
• Example test scenario
• Conclusions

3
Motivation

• The basic objective of fault diagnosis performed
  in BIST environment is to identify a fault that
  has occurred in CUT based solely on the recorded
  signatures Diagnosis of Scan Cells in BIST
  Environment, Rajski J., Tyszer J. IEEE-TC 7/99

• If the compactor is faulty then the
  fault-localising procedure will always fail and
  finally it will be concluded that the compactor
  must be faulty, indeed.

4
When does the information that confirms the
compactor correctness need to be given?

• Verification of a chip prototype,
• localisation of a faulty block,
• System on a Chip (SoC),
• performing soft repair,
• Wafer Scale Systems (WSI),
• the restructuring process,
• Functional testing of FPGA,
• shorten execution time of the diagnostic
  procedure.
• Getting the chip back for the final yield
• Another test method can be applied,
• Soft repair of compactor.

5
Traditional MISR compactor and its testing

• Applying flush test at the serial input
  SI00110011...
• Main drawbacks
• It does not test both the feedback logic and the
  AND gates,
• AND gates slow down the testing speed,
• The cost of extra hardware.

001100...
...001100...
6
No AND cutting gates approach

• Inputs are disturbed by the output vectors of
  CUT,
• Cannot be linked into scan path,
• Testing by CUT output vectors.
• Main drawbacks
• Test vectors are side effects of TPG seeding,
• Unreliable results of the test when CUT is faulty.

7
Solution - a new MISR-NOT compactor

• The essence of this new method is to keep
  constant vector W at the input of MISR-NOT
  during
• initialisation (breaking feedback)
• testing(reconnecting feedback)
• reading out the sequence that reflects the final
  signature(feedback is present)

8
Properties of a MISR-NOT compactor stimulated by
a constant vector W

• Output of a correct MISR PE00000000000000000PO1
  0100110111000010(sequence of zeroes is unusable
  in testing)
• Output of a correct MISR-NOTPO11110101100100011
  PE01010011011100001(both sequences are usable
  in testing)

9
Properties of sequences at the output of a
MISR-NOT

• A cyclic sequence always appears at the output of
  MISR-NOT independently on an input vector W.
• Fault in CUT (which changes the vector W to Werr)
  cannot disturb MISR-NOT testing and the final
  signature checking.

10
Initialisation of a MISR-NOT compactor

• By setting c10 the feedback is broken.
• In n4 clocks the register reaches the steady
  reset state R.

11
An example of testing of a MISR-NOT compactor
if P(Wref)0 then (Q1ref , Q2ref )(PE,PO) if
P(Wref)1 then (Q1ref , Q2ref )(PO,PE)
Result of testing
R - initial state of a MISR-NOTI - final state
of a MISR-NOT
12
Reading out the sequence QS which maps the
signature
Result of testing
S - signature (initial state of a MISR-NOT)S -
state of a MISR-NOT after the signature is read
13
Minimal number of clock cycles necessary to test
the MISR-NOT compactor.

• Functional testing of each flip-flop included in
  the MISR register requires driving its input with
  the following test set 00,01,10,11. These pairs
  are included in a typical test sequence
  00110011...
• It should be checked whether, during autonomous
  work of MISR-NOT, these pairs are covered by
  t-bit sequences at the outputs of each flip-flop
  of the MISR-NOT register.

14
Cyclic sequences at internal FFs of MISR-NOT

• The sequence at the output of FF can appear only
  in true/negated form due to input vector W.
• Localisation of pairs 00,01,10,11 corresponds
  to localisation of test pairs 11,10,01,00 in
  the negated sequence.
• Only two simulations for each polynomial are
  necessary.
• N clock cycles are to be added to assure that the
  test results will appear at the SO.

15
Simulation conclusions

• Among primitive polynomials of degree n where 10
  lt n lt 24, it is possible to choose such one,
  which makes possible implementation of MISR-NOT
  that requires tn2 .
• The majority of primitive polynomials makes
  possible designing MISR-NOT registers featuring a
  short test characteristic.
• If the test of length tmax is acceptable, any
  primitive polynomial can be used.

16
Test scenario with MISR-NOT compactor testing

• 1. Testing the TPG,
• 2. Forcing the TPG to hold constant the vector
  T0,
• 3. Initialising the MISR-NOT compactor,
• 4. Testing the MISR-NOT compactor,
• 5. Testing the CUT using deterministic or
  pseudorandom test stimuli,
• 6. Forcing the TPG to hold the constant vector T0
  again,
• 7. Taking out the information about the final
  signature.

17
Conclusions Part I

• A reliable information confirming compactor
  correctness is necessary
• in the diagnostic procedures while verifying the
  chip prototype,
• to achieve high-yield while testing chips at the
  wafer level,
• while reconfiguring WSI systems.
• The new test scenario with MISR-NOT compactor
  testing has been proposed.

18
Conclusions Part II

• In the case of choosing a suitable primitive
  polynomial, the number of clock cycles required
  by step 4 is n2 thus it is comparable to the
  traditional testing of n-bit MISR linked into
  scan path.
• The requirement for additional storage is
  fulfilled as an external tester is always present
  during verifying/reconfiguring the chip prototype.

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MISR-NOT generates two different sequences at SO

• The output of the last flip-flop Qn after n
  clocks of initialisation can be written
  (...(...(((w1)x ?w2x)x ?w3x2)x ?...? wi1xi)x
  ?...? wnxn-1)x (w1?w2?...?wi?...?wn)xn.
• At SO exactly two different sequences PE and PO
  appear which will depend on the parity of the
  input vector W.