332:437 Lecture 27 Packaging

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332437 Lecture 27Packaging

• Levels of packaging
• Packaging costs
• Manufacturing and labor costs
• Summary

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Levels of Packaging

• Chips semiconductor devices with ½ to 230
  million transistors
• Multi-Chip Module IC ceramic substrate with
  plated wires and multiple chips
• Sometimes hermetically sealed
• Printed Circuit (PC) Board
• Multiple layers of wiring (10 or more) with
  multiple chips or multi-chip modules mounted on
  it
• System-on-a-Chip (SoC) Entire digital system is
  on 1 chip The future of digital design
• Backplane or Mother Board Contains edge
  connectors and connects multiple PCBs avoided
  whenever possible

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Packaging Costs

• Major cost penalties for each added packaging
  level
• Increased signal delay
• Increased manufacturing cost
• Categories of IC chips -- equivalent gates
• SSI -- lt 12 gates/chip Quad 2 I/P NAND
• MSI -- lt 100 gates/chip 4-bit adder
• LSI -- lt 1000 gates/chip Register array
• VLSI -- lt 200,000 gates/chip mprocessor
• ULSI -- gt 200,000 gates/chip IBM ES9000
• 16 Processors Level 1 Cache on 1 chip

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Manufacturing Labor Costs

• Determined by
• chips used in system (preferably only 1 SoC in
  the future)
• Cost of testing entire system
• Will cost more than making the chips by 2014
• Cost of the package for the system
• Ceramic
• Epoxy

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Summary

• Levels of packaging
• Packaging costs
• Manufacturing and labor costs