STA and Timing Closure

1
STA and Timing Closure
2
Dynamic timing simulation

• - apply input stimulus to verify functionality
  and timing
• Problems
• Low fault coverage(70)
• Do not exercise all critical paths
• Too slow for million-gate design
• As a result shift in paradigm

3
New approach

• Formal verification (RTL vs final netlist)
• Static Timing Analysis for timing verification
• Some gate level simulation(dynamic simulation) to
  complement formal verification and STA.
• - Scan BIST for testing

4
Commercial STA Tools

• synopsys's Primetime, cadence Pearl
• Accuracy within 5 of spice simulation
• Need to tell the commercial tool all the timing
  exceptions(false path, multicycle path, disabled
  path)
• Relatively very fast

5
Crosstalk
6
STA with Signal Integrity-1
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STA with Signal Integrity-2
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STA Flow
2. Floorplan
1. Logic Synthesis
RTL
3. Synthesis with placement information(Physical
syn)
4. Scan/BIST/clock tree insertion
5. Place Route/ Layout
6. Parasitic extraction and delay calculation -gt
SDF file(s)
7. STA with SDF
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Timing closure

• Timing constraints do not met after layout.
• The main reason is the the wire load model
  (statistical) used during logic synthesis.
• Solution
• - Custom wire load model
• - Physical synthesis(better)