CALCE Cost Modeling

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CALCE Cost Modeling
P. Sandborn CALCE Electronic Products and Systems
Center University of Maryland Sandborn_at_calce.umd.e
du www.enme.umd.edu/ESCML
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Outline

• Web-based embedded passive and integrated passive
  device size/cost tradeoff analysis tool
• Description
• Example tradeoff study results
• Links to other tools
• Availability
• Economics of embedded resistor trimming and
  rework
• Comments on life cycle cost issues associated
  with embedded passives

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Embedded Passive Tradeoffs

• Board area decreases due to reduction in the in
  the number of discrete passive components
• Decreased wiring requirements due to the
  integration of resistors and bypass capacitors
  into the board
• Increased wiring density requirements due to the
  decreased size of the board
• Increased number of boards fabricated on a panel
  due to decreased board size
• Increased board cost per unit area
• Increased board fabrication waste
• Decreased board yield
• Decreased board fabrication throughput
• Decreased assembly cost
• Decreased overall assembly yield
• Decreased assembly level rework

WHEN DO EMBEDDED PASSIVES REDUCE SYSTEM COSTS?
not a simple tradeoff
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Embedded Passives Tradeoff Model
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Modeling Assumptions

• Embedded resistors fabricated on wiring layers
  via screening, plating or addition of layers
  (Ohmega-Ply)
• Discrete singulated embedded capacitors are
  fabricated on a dedicated capacitor layer
• Bypass capacitors embedded through dielectric
  substitution into an existing reference plane
  layer pair
• Every cost that would be the same for
  conventional and embedded implementations is
  ignored (i.e., non-embeddable components,
  functional test)
• Conversion of double to single sided boards not
  modeled

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Model Features

• Supports resistor, capacitor, and mixed resistor
  and capacitor embedding
• Board fabrication throughput treated via profit
  margins
• Bypass and non-bypass capacitors supported
• Board re-sizing (option to fix or float)
• Routing estimation (board layer requirements)
• Board panelization (homogeneous layout only)
• Discrete passive yields
• Discrete passive assembly costs and yields
• Discrete passive assembly rework
• Supports full Monte Carlo uncertainty analysis
• Supports local file system Save and Load
• Includes plotting and printing
• Includes help page defining all input fields

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Integrated Passive Device (IPD) Tradeoffs
Over 400 IPDs in the library (Panasonic, Bourns,
CTS)
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Analysis Examples
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Fiber Channel Card

• 12 x 18 inch board
• 12 layers
• Embeddable Passives
• 242 bypass capacitors
• 610 resistors

Conventional Solutions
Specific Solution
General Solution
Relative System Cost ()
18 x 24 inch panel
Bands represent all possible solutions. Actual
answer depends on knowledge of routing statistics
for the application
16 x 20 inch panel
of Embeddable Resistors Embedded
(Up to and including 10 Kohms)
MacDermid M-Pass
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Fiber Channel Card
Conventional Solutions
3M C-ply 1.12 embeddable bypass
capacitors/square inch
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NEMI Hand-Held Emulator
Conventional Board
Relative System Cost ()
63 boards/panel
70 boards/panel
of Embeddable Resistors Embedded
MacDermid M-Pass
(Up to and including 10 Kohms)
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NEMI Hand-Held Emulator
3M C-ply 23 embeddable bypass capacitors/square
inch
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General Bypass Capacitor Embedding Results
Bypass capacitors only single layer substitution

• Capacitor Crossover Density the density of
  capacitors at which it becomes cost effective to
  use embedded capacitors for the specific
  application.
• Assumptions (for this plot)
• The number of boards fabricated on a panel is
  constant as capacitors were embedded
• The number of board layers required for routing
  is constant as capacitors were embedded
• Actual capacitor densities
• Fiber Channel Board 1.12 caps/in2
• Picocell Board 2.76 caps/in2
• NEMI Hand Held Emulator 23.44 caps/in2
• Avionics Functional Demonstrator 3.34 caps/ in2
• Telecom Board 3.78 caps/ in2

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Example Tradeoffs Using IPDs (NEMI Hand Held
Emulator)
Panasonic EXA-NPE 221 (8 220pF caps) Panasonic
EXB-28V 512 (4 5.1KW res) Panasonic EXB-28V 562
(4 5.6KW res)
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Cost only costs associated with passive
procurement and assembly board price

• 2.17 x 2.17 in
• 107 applicable (replaceable) capacitors
• 174 applicable resistors

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Example Tradeoffs Using IPDs (Fiber Channel Card)
CTS 744 104 (4 100KW res) CTS 744 823 (4 82KW
res) Panasonic EXB-28V 562 (4 5.6K res) Panasonic
EXB-28 511 (4 510W res) Panasonic EXB-28V 510 (4
51W res)
Cost only costs associated with passive
procurement and assembly board price

• 12 x 18 in
• 242 applicable (replaceable) capacitors
• 610 applicable resistors

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Links to Other Tools

• Spreadsheets
• Input BOM from a spreadsheet CSV file
• Output plots to spreadsheet CSV files
• Cadence Allegro
• Input BOM and board description from Allegro
• Foresight SavanSys
• Parameterization of SavanSys process flow results
  to populate web-based model fabrication and
  assembly cost fields (incomplete)

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Availability

• Web-based tradeoff tool is presently available
  to
• AEPT consortium members
• University of Maryland CALCE consortium members
• (50 organizations today)
• Application-specific analyses available through
  CALCE Laboratory Services
• Future availability plan
• A proposal has been made to the CALCE Consortium
  to make the tool available to a broader group of
  organizations

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Economic Applicability of Embedded Resistor Trim
and Rework

• The successful use of embedded resistors in many
  applications will require that the fabricated
  resistors be trimmed prior to lamination into
  printed circuit boards to attain required design
  tolerances.
• Depending on the application, it may also be
  prudent to consider reworking resistors with
  initial values that are too large (un-trimmable
  resistors) and resistor trimming errors.

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• We modeled the resistor/board yield coupled with
  a cost model of the trim and rework processes to
  identify conditions under which embedded
  resistors in applications should be
• Not trimmed or reworked (non-conforming boards
  are scrapped)
• Trimmed but not rework
• Both trimmed and reworked
• These cases are evaluated as a function of the
• Design tolerance required for the resistors
• Accuracy with which the embedded resistors can be
  formed
• Yield of the trimming process

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Distribution of Fabricated Embedded Resistors
K. Fjeldsted and S. L. Chase, Embedded passives
Laser trimmed resistors, CircuiTree, pp. 70-76,
March 2002.
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Embedded Resistors are Fabrication Down and
Trimmed Up
Lowest Trimmable Resistor
Application Target
HSL
LSL
Frequency
Fabrication Target
Resistance
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Resistor Rework
Resistance of embedded resistors can be lowered
by adding additional material to the surface of
the component.
How do we recover these resistors?
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Modeling Process to Obtain Trim/Rework
Applicability Analysis
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Variation in Resistor Dimensions
Terminal
Resistor
Width
sw
sw
Length
Also the thickness is allowed to vary (st)
All variations are assumed to be
resistor-to-resistor variations (not variations
within a single resistor)
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Applications Considered
 
Quantities of embedded resistors
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Regions of Applicability
12 x 18 in 1 boards/panel 610 resistors/panel 2.8
embedded res/in2
Trimming rework
No trimming, no rework (centered process)
2.27 x 6.87 in 18 boards/panel 1260
resistors/panel 4.5 embedded res/in2
Trimming, no rework
2.17 x 2.17 in 60 boards/panel 4410
resistors/panel 15.6 embedded res/in2
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No thickness (material property) variation
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Thickness (Materials Property) Variation
10 thickness variation (one standard deviation)
5 thickness variation (one standard deviation)
Trimming rework
Trimming rework
No trimming, no rework (centered process)
No trimming, no rework (centered process)
Trimming, no rework
Trimming, no rework
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Characterizing the Boundary Between Trimming and
Not Trimming
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Summary

• It must be reiterated that due to the opposing
  nature of many of the effects outlined in this
  presentation, the overall economic impact of
  replacing discrete passives with integral
  passives, in general, yields application-specific
  guidelines instead of general rules of thumb
• In addition to the direct effects on system cost
  discussed herein, there are many other life
  cycle effects on the system cost. These effects
  include
• System reliability
• Performance
• End-of-life options
• Design overhead
• Upgradability
• Obsolescence
• Clearly defined regions of applicability for
  trimming and rework can be identified as a
  function of design tolerance, and standard
  deviation size in x, y, and z dimensioning
  (material property variation)
• The regions are approximately application
  independent, i.e., independent of resistor
  density on the panel

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Further Information

• Web-based tradeoff tool development,
  implementation, and additional example analyses
• P. A. Sandborn, B. Etienne, and G. Subramanian,
  Application-Specific Economic Analysis of
  Integral Passives, IEEE Trans. on Electronics
  Packaging Manufacturing, Vol. 24, No. 3, pp.
  203-213, July 2001.
• Embedded Resistor Trim and Rework Analysis
• P. Sandborn, An Assessment of Embedded Resistor
  Trimming and Rework, submitted to IEEE Trans. on
  Electronics Packaging Manufacturing., October
  2002.
• Life cycle cost impact of embedded passives
• P. Sandborn, "The Economics of Embedded
  Passives," in Integrated Passive Component
  Technology, R. Ulrich and L. Schaper editors,
  IEEE Press, 2002.