System Design Space Exploration

1
System Design Space Exploration

• Waseem MUHAMMAD
• Masters 2 STIC Systèmes Embarqués
• Stagiaire LabSoC Télécom Paris
• Responsable Renaud PACALET

2
Introduction

• SoC design phases
• Specifications
• Design Space Exploration
• Refinement
• Implementation
• Context of internship
• Goal- Faster design space exploration
• Mean- Faster system simulation
• Objectives-
• A library of abstract architecture models
• A modeling language to represent applications
• A methodology for abstract modeling of
  applications

3
Methodology

• Key Ideas
• Separation of architecture and application models
• Data processing abstraction
• Generic parameterized architecture models
• Formal analysis techniques
• Application Models
• Task Modeling Language (TML)
• Architecture Models
• SystemC architecture components library

4
Related work

• SPADE SESAME
• Separation of application and architecture
• Applications models KPN Models
• Architecture models generic abstract components
• OCAPI-xl Library
• Separation of functionality and architecture
• Flexible partitioning choice
• Automatic code generation for software and
  hardware
• ArchAn simulator
• Cycle accurate hardware models C and Estérel
• Task modeling language for applications
• Mix of applications and architecture
• Simulation based tools, No formalism

5
Task Modeling Language (TML)

• An abstract application modeling language
• Underlying architecture independent task models
• Abstract TML instructions
• EXEC (execute)
• RD (read )
• WR (write)
• REQ (request)
• NOTIFY
• WAIT
• Control structures
• IF--ELSE , REPEAT

6
Task Modeling Language (TML)

• Virtual channels and events
• Global declaration
• Virtual channel task to task data exchange, one
  reader one writer
• Event task to task control exchange, one
  notifier one listener (unicast)
• General purpose language constructs
• Local variable declarations
• Operators (unary, arithmetic, logical, bitwise)
• Pragmas

7
TML Instructions

• EXEC
• No. of operation performed by a task while
  executing
• Three variants EXECI, EXECF, EXECC
• Behavior can be modified using pragmas
• Example EXECI 200
• REQ
• Internode or intranode task spawning
• With or without parameter
• Example REQ NOISE_SUP(300)

No. of operations
Parameter
Task ID
8
TML Instructions (contd)

• RD / WR
• Data exchange instructions
• Read / write No. of samples to/from a virtual
  channel
• Global channel declaration channel ch0 2
  BRNBW
• Virtual channel types
• BR-NBW Blocking Read / Non-blocking Write
  (infinite FIFOs, KPN)
• BR-BW Blocking Read / Blocking write (finite
  FIFO)
• NBR-NBW Non-blocking Read / Non blocking Write
  (shared memory)
• Example RD 32 ch0 , WR 20 ch2

type
size
channel ID
No. of samples
9
TML Instructions (contd)

• NOTIFY
• Event notification semantics
• Global event declaration event DCT_DONE
• Example NOTIFY DCT_DONE
• WAIT
• Wait for an input event
• Example WAIT DCT_DONE
• Parameter value passing semantics (near future)

Event name
10
Example Task Models in TML
11
Task Scheduler Model

• SystemC No RTOS services
• A simplified model
• Priority based dynamic scheduling
• Task Control Block (TCB)
• State Transitions
• A REQ a task with low priority
• B next task execution
• C REQ a task with high priority
• D BR or BW blocked
• E BR or BW released
• F END TASK

12
Architecture Components

• Multi-master multi-slave system
• Generic SystemC abstract models
• Parameterized
• Masters CPU with or without OS
• Computation Nodes CPU, HWA
• Slaves HWA, RAMs, I/O devices
• Computation services
• Storage services
• Non-deterministic services
• Bus model
• Communication services
• Transaction based communication
• Arbitration schemes
• Bridges

FIFOs
CPU2
CPU 1
BUS
I/O Peripheral
Memory
HWA
13
Simulation

• Compilation
• Offline TML compiler
• Flex and Bison tools
• Mapping
• Mapping of application on the architecture
• Elaboration time
• Channel to device mapping
• Task to device mapping
• Task priorities
• Simulation
• Cycle based simulation
• Single master clock

14
Conclusion

• Simulation optimization
• TML Not a new language, A new methodology
• Specification for TML are not complete today
• Open questions!
• Future directions
• Static Formal validation
• Real time tasks with complex RTOS model
• Complex bus traffic models
• Cache memories
• Heterogeneous clocks
• PhD research topic

15
Thank you