Architectures and Implementations of

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• Architectures and Implementations of
• Low-Density Parity Check
• Decoding Algorithms
• Engling Yeo, Borivoje Nikolic, and Venkat
  Anantharam
• Department of Electrical Engineering and Computer
  SciencesUniversity of California, Berkeley, CA
  94720, USA

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Background Iterative Codes
4 dB
C. Berrou and A. Glavieux, "Near Optimum Error
Correcting Coding And Decoding Turbo-Codes,"
IEEE Trans. Comms., Vol.44, No.10, Oct 1996. S.
Chung G.D. Forney, T.J. Richardson, and R.
Urbanke, On the design of low-density
parity-check codes within 0.0045 dB of the
Shannon limit, IEEE Communications Letters,
vol.5, (no.2), IEEE, Feb. 2001. pp.58-60.
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Outline

• LDPC Codes
• Soft Decoding of LDPC Codes
• Parallel vs. Serial Architectures
• Platforms
• Methods for Code Construction

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Low Density Parity Check Codes (LDPC)
CHECK NODES
VARIABLE NODES
- R. G. Gallager, IRE Trans. Info. Theory, Vol.
8(1962) p. 21

• LDPC representation by bi-partite graph.
• Decoding by message computation and relay along
  edges
• Iteratively improved estimates of log-likelihood
  ratios
• Example code

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Outline

• LDPC Codes
• Soft Decoding of LDPC Codes
• Parallel vs. Serial Architectures
• Platforms
• Methods for Code Construction

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Message from Variable n to Check m
CHECK NODES
m
1
2
3
R2n
R1n
Qnm
R3n
VARIABLE NODE
n
Decoder input
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Message from Check m to Variable n

• Signed magnitude representation
• MSB represents parity information

CHECK NODE
m
Q3m
Q1m
Rnm
Q2m
VARIABLE NODE
n
1
2
3
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Hardware for Computation of Rmn
b Wordlength of messages
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Outline

• LDPC Codes
• Soft Decoding of LDPC Codes
• Parallel vs. Serial Architectures
• Platforms
• Methods for Code Construction

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Parallel Architecture of LDPC decoders
A. Blanksby and C. J. Howland, A 220mW 1-Gbit/s
1024-Bit Rate-1/2 Low Density Parity Check Code
Decoder, Proc IEEE CICC, Las Vegas, NV, USA, pp.
293-6, May 2001.
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Serial Architecture of LDPC decoders
G. Al-Rawi, J. Cioffi, and M. Horowitz,
Optimizing the mapping of low-density parity
check codes on parallel decoding architectures,
Proc. IEEE ITCC, Las Vegas, NV, USA, pp.578-86,
Apr 2001.
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Outline

• LDPC Codes
• Soft Decoding of LDPC Codes
• Parallel vs. Serial Architectures
• Platforms
• Methods for Code Construction

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Decoding with Software Approach

• General purpose microprocessors and Digital
  Signal Processors (DSP)
• Limited number of Processing Elements (ALUs)
• Serial Architecture
• Few hundreds of kbps throughput
• Design, simulate, and perform comparative
  analysis of LDPC codes
• Low throughput applications with fast time to
  market element

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Decoding with Hardware Approach

• Parallel architecture
• Power and throughput efficiency
• FPGA
• Parallel adders and table lookups
• Need to fit PEs and routing onto single FPGA die
• Existing implementations with serial architecture
  limited to 56Mbps throughput
• M. M. Mansour and N. R. Shanbhag,
  Memory-efficient turbo decoder architectures for
  LDPC codes, Proc. IEEE SIPS 2002, San Diego, CA,
  Oct. 2002.
• T. Zhang and Keshab Parhi, A 56Mbps
  (3,6)-Regular FPGA LDPC Decoder, Proc. IEEE SIPS
  2002, San Diego, CA, Oct. 2002.

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Decoding with Hardware Approach

• Custom ASIC
• Parallel implementation demonstrated with 1Gbps
  throughput
• A.J. Blanksby and C.J. Howland, A 690-mW
  1-Gb/s 1024-b, rate-1/2 low-density parity-check
  code decoder, IEEE Journal of Solid-State
  Circuits, vol.37, (no.3), (Proceedings of the
  IEEE 2001 Custom Integrated Circuits Conference,
  San Diego, CA, USA, 6-9 May 2001.) IEEE, March
  2002. p.404-12.
• Routing congestion
• Logic density is 50
• Design not scalable to codes with larger block
  sizes

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Solving Routing Congestion in Hardware

• Serial architecture with groups of parallel
  optimized processing elements
• Full utilization of pipelined hardware with
  alternating blocks
• E.g. 128x parallelism in commercial IP
  (FlarionTM)
• Further memory reduction through staggered
  decoding schedule
• E. Yeo, P. Pakzad, B. Nikolic, and V.
  Anantharam, "High throughput low-density
  parity-check architectures," Proc. IEEE
  Globecom2001, San Antonio, TX, pp.3019-24, Nov
  2001.

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Platform vs. Throughput Summary
107
108
109
103
105
106
104
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Outline

• LDPC Codes
• Soft Decoding of LDPC Codes
• Parallel vs. Serial Architectures
• Platforms
• Methods for Code Construction

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Density Evolution

• Density Evolution
• Very good codes (lt 0.0045dB from theoretical
  bound)
• Large variable edge degree ( 100)
• Large block size (107)
• Cayley and Ramanujan Graphs
• Unstructured interconnects
• Algebraic Constructions
• Cyclic or quasi-cyclic properties
• Use of shift registers
• Parallel implementation has to address sparse
  code / interconnect issue.

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Summary

• Difficulties with routing or memory requirement
• Parallel architectures are optimal for power/
  throughput efficiency
• Different platforms (microprocessor/FPGA/ASIC)
  offers possibilities for various applications
• Methods for code construction need to consider
  implementability

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Low Density Parity Check Codes (LDPC)

• LDPC representation by bi-partite graph.
• Non-zero entries in each
• Row m represent the set of bits that are
  connected to check m, n(m) n Hm,n 1
• Column n represent the set of checks that are
  connected to bit n. m(n) m Hm,n 1 is

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Sparse Graph
Limited spatial locality between input
edges Rearrangement of nodes has limited effect
in improving spatial locality
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Hardware Pipelining of serial architecture
STALL!!

• Traditional DSP Algorithms
• e.g. FFT, Digital Filters
• Throughput increases
• High spatial locality