Automated Design of MisalignedCarbonNanotubeImmune Circuits

1
Automated Design of Misaligned-Carbon-Nanotube-Im
mune Circuits

• Nishant Patil
• Jie Deng
• H.-S. Philip Wong
• Subhasish Mitra
• Departments of Electrical Engineering Computer
  Science
• Stanford University

2
Key Message

• Misaligned-CNT-Immune Logic Design

Carbon Nanotubes (CNTs) on Quartz Prof. Zhou,
USC

• Immune to ANY number of misaligned CNTs
• Arbitrary logic function
• Formal correctness proof

3
CNFET Transistor Layout
Lithographic Gate
Oxide
CNT doped region
CNT undoped region
Substrate
CNT undoped region
Side View
Top View

• Ideal CNFET circuits vs. 32nm CMOS
• 13X EDP gain Deng et al., ISSCC 07

4
Perfect CNFET Inverter Layout
P doped Semiconducting CNTs
Vdd
64nm 4?
PFET
Input
4nm
Gates
Output
NFET
N doped Semiconducting CNTs
Gnd
5
CNFET Fabrication Process

• Define cell regions
• on substrate
• Etch CNTs outside
• cell regions
• Define gates and contacts
• Chemically dope CNTs

6
CNFET Imperfections Misaligned CNTs
Vdd
Vdd
Vdd
A
Short
A
B
B
A
Out
C
D
A
B
B
Out
Gnd
Out
A
C
Wanted A? B? Got Short
Wanted A?C? B?D? Got A?C? B?D? A?D?
A
D
B
B
Gnd
Wanted (AC) (BD) Got (BD)
Gnd
7
Misaligned-CNT-Immune NAND Design

• Grow CNTs
• Define gates and contacts
• Chemically dope P-type region
• Chemically dope N-type region
• Etch

Undoped region enables misaligned-CNT-immune
design

• Formal approach generalized for arbitrary
  functions

8
Misaligned-CNT-Immune NAND Design

• Grow CNTs
• Define gates and contacts
• Etch CNTs
• Chemically dope P-type region
• Chemically dope N-type region

Etched region enables misaligned-CNT-immune design

• Formal approach generalized for arbitrary
  functions

9
Generalized Algorithms for Any Function

• Input Layout design
• Output
• Determine Misaligned-CNT-Immune?
• Input Logic function
• Output
• Misaligned-CNT-Immune layout design

10
Misaligned-CNT-Vulnerable NAND Pull-up
Intended Function A or B
C
C
C
Contact
D
D
D
GA
A
GA
D
Doped
D
D
D
GB
B
GB
D
Gate A
D
D
D
Gate B
C
C
C
Contact
Implemented Function A or B or (A AND B) or 1
1 ! A or B
Path 1 C-D-A-D-C fn A Path 2 C-D-B-D-C fn
B Path 3 C-D-A-D-B-D-C fn A B Path 4
C-D-C fn 1
11
Misaligned-CNT-Immune NAND Pull-up
Path 1 C-D-A-D-C fn A Path 2 C-D-B-D-C fn
B Path 3 C-D-A-D-B-C fn A B Path 4
C-D-B-UD-A-D-C fn 0
Contact
Doped
UD
GA
GB
Doped
Contact
Contact
Intended Function A or B Implemented Function A
or B or (A and B) or (A and B and 0) A or B
Doped
Undoped
Gate B
Gate A
Doped
Contact
12
Misaligned-CNT-Immune Arbitrary Function
A (B C)(D E)
Undoped regions
Vdd/ Gnd Contact
CNTs
C
B
A
Gates
Intermediate Contact
D
E
Output Contact

• Immune to ANY number of misaligned CNTs
• Arbitrary logic function
• Formal correctness proof (Details in paper)

13
Simulation Results

• Misaligned-CNT-Immune vs. Misaligned-CNT-Vulnerab
  le
• CNFET model Deng Wong, SISPAD 06
• 10 accuracy vs. experimental data Amlani IEDM
  06

Significantly less penalty vs. traditional defect
tolerance
14
Conclusion

• Misaligned-CNT-Immune design
• Arbitrary logic functions
• Immune to ANY number of misaligned CNTs
• Formal correctness proof
• Efficient
• Future Work
• Metallic-CNT-immune circuits
• High CNT density

15
Thank You