Homework 5 Solutions

1
Homework 5 Solutions

• 6.3 Move the lw into the branch delay slot. Need
  to adjust the offset since the modified code
  increments 3 before its use.
• Loop addi 3, 3, 4
• beq 3, 3, 4
• lw 2, 96(3)
• 6.4 Let the instructions be labeled A, B, C, D
  in order. The instruction at the arrow head
  depends on the one at the tail.
• RAR Dependencies RAW Dependencies WAR
  Dependencies WAW Dependencies
• A B (5) A
  B A B
• A D (4) A C
• B C (2) A D
• B C (5) B D
• C D (2)

Only RAW dependencies may result in hazards in
the 5-stage pipeline. Of these, the first two
and the last can be solved by forwarding. The
third (between A and D) can be solved simply by
appropriate register file design (our default
design).
6.19 In the sw,lw code sequence the only
register-register dependency is the innocuous RAR
of register 2. However, there is a RAW
dependency between the two instructions since the
sw is writing to the same memory location that
the lw will read. On the MIPS pipeline this will
not be a hazard, since both the read and write of
memory occur in the same stage, so the lw which
follows sw will read the correct value written
by the store.
620 The earliest the lw has the correct value
from memory is when it is in the MEM/WB register,
following the memory read. At this time, the sw
is in the EX/MEM register, having read the stale
value of 2 in the ID stage. During the next
cycle the sw will write to memory. Rather than
allowing the incorrect stale value to be written,
we must forward the value obtained by the lw to
the input of the MEM and store that instead. (See
figure on next page).
2

• EX/MEM
  MEM/WB

WRITE
Value read by lw from MEM
ADDRESS
MEM
M U X
a
b
Forwarding Equation If MEM/WB has a lw
instruction with destination register RD and
EX/MEM has a sw instruction with data operand
source register RT and RTRD (and neither is
zero) then MUX should pass b else it should
pass a.
DATA
Stale value of 2 read by sw in ID stage
Forwarding Unit
3
Homework 5 Solutions (page 3/12)

• The code on page 490 for stalling stalls the
  pipeline when it sees a lw in the ID/EX register
  whose destination register
• matches either of the source registers in the
  instruction in the IF/ID register. This condition
  will be satisfied when the given
• lw, sw sequence is executed. However, we do not
  want the pipeline to stall in this case, since we
  can take care of the potential
• hazard by forwarding. So we change the equation
  to include the condition AND NOT sw in the IF/ID
  stage.
• 6.28
• slt 1, 8, 9 Set temp reg. 1 to 1
  if 9 is larger
• movn 10, 9, 1
• movz 10, 8, 1
• 7. There are 3 cases when these instructions can
  interfere destructively.
• Case 1 Case 2 Case 3
• A add 3, 4, 5 A add 3, 4, 5 A add 3,
  8, 9
• B sw 3, 1000(6)
  C IP
  C add 3, 4, 5
• B sw 3, 1000(6)
  B sw 3, 1000(6)
• In case 2, IP is an independent instruction that
  does not write to register 3. Clearly, case 1
  will require forwarding from 1 stage ahead in the
  pipeline, while case 2 will require forwarding
  from 2 stages ahead in the pipe. Case 3 handles
  the situation when both A and C may be
  simultaneously trying to forward their result to
  B. In this case we must ensure that B uses the
  value from C and not from A.

4
Solution 1 Different circuits to handle case 1
and case 2
Result of add

• Case 1

cntrl
EX/MEM
MEM/WB
Stale value read from 3
ADDR
MEM
M U X
DATA IN
add
sw
Case 2
ID/EX
MEM/WB
EX/MEM
EX
Result of add
Stale value read from 3
ADDR
MEM
M U X
DATA IN
Note Together these will handle case 3 correctly
as well
add
sw
C
5
Solution 2 Single MUX with 3 inputs for all cases
ID/EX

MEM/WB
EX/MEM
Result of add
Stale value read from 3
ADDR
MEM
M U X
DATA IN
sw
add
IP
ID/EX
MEM/WB
EX/MEM
EX
Result of add
Stale value read from 3
ADDR
MEM
M U X
DATA IN
Note Together these will handle case 3 correctly
as well
Result of add
add
sw
add
6
Q1 (a) Datapaths for sw rt, d(rs) (cycles 3 and
later)
Cycle 3 ALUout A SE(d) Cycle
4 MEMALUout B
MEM WRITE
PC
ADD
IR
MEM
REG
ALU
(rs)
ALUout
A
ADDR
B
DATA IN
MDR
d
SE
ltlt
(rt)
7
Cycle 5 ALUout MDR B Cycle 6
REGrd ALUout
Cycle 3 ALUout A SE(d) Cycle
4 MDR MALUout
REGI WRITE
MEM READ
PC
ADD
IR
MEM
REG
rd
ALU
ALUout
A
(rs)
ADDR
(rt)
B
MDR
d
DATA OUT
d
SE
ltlt
MUXes whenever we have two or more signals to
same input
8

• 10 (a) Show the forwarding paths necessary to
  allow the sequence of instructions A, B to
  execute correctly with the minimum number of
  stalls. Indicate how many stall cycles are needed
  if any. Clearly shown and label all the inputs
  to the MUXes in your design.
• A lw 3, (4) B lw 5, (3)

old 3
MUX
Mem ADDR
Value read from MEM
A
B
9
(b) Repeat part (a) for the instructions A add
3, 4, 5 B lw 6, (3)
Earliest that result of A is available When A is
in EX/WB Register Latest that B needs the
result of A When B is in ID/MEM register. Hence
1 stall needed.
old 3
MUX
P C
Mem ADDR
ID
EX
MEM
WB
IF
B
A
Result of add
10

• (c) Repeat part (a) for the instructions .
• A add 3, 4, 5 B add 6, 7, 8
  C add 9, 3, 6

Need to forward from A to C (A in EX/WB register
and C in ID/MEM register) and from B to C (B in
EX/WB register and C in MEM/EX register).
Forwarded result of A
Stale 3 value read by C
B
A
C
MUX
P C
ID
EX
WB
IF
MUX
Stale 6 value read by C
Result of A or B
C
B
MEM
11
(d) Repeat part (a) for the instructions
A add 3, 4, 5 B add 6, 7, 8
C sw 6, (3)
Require 1 stall cycle between B and C
Stale value of 6
MUX
P C
ID
EX
MEM
WB
IF
Result of B
3 (correct value) read when A was in EX/WB and C
was in IF/ID
C reads correct value of 3
A
B
C
C
B
Result of B must be forwarded to C