PARBIT - Partial Bitfile Configuration Tool

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PARBITPartial Bitfile Configuration Tool

• Edson L. Horta
• (horta_at_arl.wustl.edu)
• Washington University, Applied Research Lab
• August 15, 2001
• Supported by NSF ANI-0096052
• Xilinx Inc. and CNPq (Brazil)

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Motivation

• RECATS

• FPX

Single chip ATM Switch VIRTEX FPGA Partial
Reconfigurable www.lsi.usp.br/recats
VIRTEX FPGA Partial Reconfigurable Dynamic
Hardware Plugin http//www.arl.wustl.edu/arl/proje
cts/fpx
Mutual Need tool to generate partial
configuration files for VIRTEX FPGA
PARBIT
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VIRTEX Architecture

• Resources
• CLBs
• IOBs
• Block SelectRAMs
• Clocks
• Configuration
• bitstream configuration bitfile
• configuration columns
• Center
• CLB
• IOB
• Block SelectRAM Interconnect
• Block SelectRAM Content

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VIRTEX Architecture

• Configuration Columns

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PARBIT Tool - Introdution

• A Tool that transforms configuration bitfiles to
  generate partial configuration bitfiles with
  hardware realocation
• Command-line interface
• Environment
• Windows (Cygwin)
• Unix
• Devices supported
• XCV50E, XCV100E, XCV200E, XCV300E, XCV400E,
  XCV405E, XCV600E, XCV812E, XCV1000E, XCV1600E,
  XCV2000E,XCV2600E, XCV3200E.
• http//www.arl.wustl.edu/arl/projects/fpx/parbit/

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PARBIT Tool - Introdution
FPGA Type Coordinates Shutdown Configuration Port
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PARBIT Tool - Introdution

• Utilization
• parbit option original partial target
• Input Files
• option user parameters
• original Dynamic Hardware Plugin (DHP) bitstream
  
• target infrastructure bitstream
• Output File
• partial generated partial bitstream
• Generating the input bitstream files
• Xilinx Tools
• Constraints commands in the UCF file

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PARBIT Tool - Introdution

• Original Bitstream File
• DHP User Module
• Locks the interface signals to the
  infrastrucuture
• Locks the area of user logic
• Target Bitstream File
• Infrastructure Logic
• Locks the interface signals to the DHP User
  Module
• Allocate blank areas (targets) to download new
  DHP Modules

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PARBIT Tool Original Bitstream

• Dynamic Hardware Plugin (DHP) confined in a
  rectangular region
• PARBIT parameters
• Start Row and Start Col
• End Row and End Col

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Original Bitstream - DHP Module
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DHP User Module - Example

• 8 stages of combinatorial function, with
  registered outputs
• Connects to gas_dhp entity buses (din, dout)
• Consumes 32 CLBs

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DHP Module - VHDL
library IEEE use IEEE.std_logic_1164.all --
Top Level Entity of DHP also specifies -- pins
so that a FPGA can be routed and placed entity
gask_dhp is port( gask_in in
std_logic_vector(3 downto 0) gask_clk in
std_logic gask_out out std_logic_vector(3
downto 0)) end gask_dhp library IEEE use
IEEE.std_logic_1164.all USE ieee.std_logic_arith
.ALL -- Entity of a Dynamic Hardware
Plugin entity dhp is port( din in
std_logic_vector(3 downto 0) clk in
std_logic dout out std_logic_vector(3 downto
0)) end dhp
architecture dhp_arch of dhp is -- The User's
Module Logic goes HERE signal stage0_sig
std_logic_vector (3 downto 0) signal stage1_sig
std_logic_vector (3 downto 0) signal stage2_sig
std_logic_vector (3 downto 0) signal stage3_sig
std_logic_vector (3 downto 0) signal stage4_sig
std_logic_vector (3 downto 0) signal stage5_sig
std_logic_vector (3 downto 0) signal stage6_sig
std_logic_vector (3 downto 0) begin Stage0
process (clk) begin if(clk'event AND clk
'1') then stage0_sig(0) lt NOT din(0) OR
din(1) stage0_sig(1) lt din(2) XOR din(0)
stage0_sig(2) lt NOT din(3) NOR din(2)
stage0_sig(3) lt din(1) AND din(0) end if
end process
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DHP Module - VHDL
-- The User's Module is the Main Component of the
Module design component dhp is port( din
in std_logic_vector(3 downto 0) clk in
std_logic dout out std_logic_vector(3 downto
0)) end component signal ding,doutgstd_logi
c_vector(3 downto 0) begin D dhp port
map(ding,gask_clk,doutg) -- Specifies the same
Flops in the same location G for i in 0 to 3
generate INGASK FD port map( gask_in(i),
gask_clk, ding(i))
Stage1 process (clk)
Stage7 process (clk) begin if(clk'event AND
clk '1') then dout(0) lt stage6_sig(2) NAND
stage6_sig(0) dout(1) lt NOT stage6_sig(3)
NAND stage6_sig(3) dout(2) lt NOT
stage6_sig(0) XOR stage6_sig(2) dout(3) lt
stage6_sig(1) NAND stage6_sig(1) end if end
process end dhp_arch architecture
gask_dhp_arch of gask_dhp is component FD
port( D in std_logic C in std_logic
Q out std_logic) end component
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DHP Module - VHDL and UCF File
gask_dhp.ucf PINS NET gask_clk LOCB8 NET
gask_inlt0gt LOCC8 NET gask_inlt1gt LOCB7 NET
gask_inlt2gt LOCA6 NET gask_inlt3gt LOCD8 NET
gask_outlt0gt LOCF3 NET gask_outlt1gt LOCD1 NET
gask_outlt2gt LOCG3 NET gask_outlt3gt LOCF5
OUTGASK FD port map( doutg(i), gask_clk,
gask_out(i)) end generate end
gask_dhp_arch

• Include Region for DHP User Module
• INST /D LOCclb_r3c6clb_r6c7
• FLOPS
• INST /OUTGASK_0 LOCclb_r3c5.s0
• INST /OUTGASK_1 LOCclb_r4c5.s0
• INST /OUTGASK_2 LOCclb_r5c5.s0
• INST /OUTGASK_3 LOCclb_r6c5.s0
• INST /INGASK_0 LOCclb_r3c8.s1
• INST /INGASK_1 LOCclb_r4c8.s1
• INST /INGASK_2 LOCclb_r5c8.s1
• INST /INGASK_3 LOCclb_r6c8.s1

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DHP Module FPGA Editor (XCV50E)
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DHP Module FPGA Editor (XCV50E)
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PARBIT Tool Target Bitstream

• Infrastructure with target regions reserved for
  DHP modules insertions
• PARBIT parameters
• Target Locations (Row, Col)

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Target Bitstream - Infrastructure Module
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Infrastructure Module - VHDL

• library IEEE
• use IEEE.std_logic_1164.all
• -- Top Level Entity of Infrastructure
• entity gask_inf is port(
• gask_in in std_logic_vector(3 downto 0)
• gask_clk in std_logic
• gask_out out std_logic_vector(3 downto 0))
• end gask_inf
• library IEEE
• use IEEE.std_logic_1164.all
• -- Each gask_io module provides an input/ouput
• -- interface between the infrastructure and
  module
• entity gask_io is port(
• di in std_logic
• clk in std_logic
• qo out std_logic)

architecture gask_io_arch of gask_io is
component FD port( D in std_logic C in
std_logic Q out std_logic) end
component signal q0 std_logic -- Each
gas_io module has two Flops, one -- on each edge
of DHP begin GASKIN FD port map(D gt di,
C gt clk, Q gt q0) GASKOUT FD port map(D
gt q0, C gt clk, Q gt qo) end
gask_io_arch
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Infrastructure Module - VHDL and UCF File
gask_inf.ucf PINS NET gask_clk LOCB8 NET
gask_inlt0gt LOCC8 NET gask_inlt1gt LOCB7 NET
gask_inlt2gt LOCA6 NET gask_inlt3gt LOCD8 NET
gask_outlt0gt LOCF3 NET gask_outlt1gt LOCD1 NET
gask_outlt2gt LOCG3 NET gask_outlt3gt LOCF5

• architecture gask_inf_arch of gask_inf is
• component gask_io port(
• di in std_logic
• clk in std_logic
• qo out std_logic)
• end component
• begin
• G for i in 0 to 3 generate
• -- Bus contains an array of gask_io modules
• GASK gask_io port map(
• gask_in(i),
• gask_clk,
• gask_out(i))
• end generate

Exclude Region for DHP User Module CONFIG
PROHIBITCLB_R3C6CLB_R6C7 FLOPS INST
/GASK_0/GASKOUT LOCclb_r3c5.s0 INST
/GASK_1/GASKOUT LOCclb_r4c5.s0 INST
/GASK_2/GASKOUT LOCclb_r5c5.s0 INST
/GASK_3/GASKOUT LOCclb_r6c5.s0 INST
/GASK_0/GASKIN LOCclb_r3c8.s1 INST
/GASK_1/GASKIN LOCclb_r4c8.s1 INST
/GASK_2/GASKIN LOCclb_r5c8.s1 INST
/GASK_3/GASKIN LOCclb_r6c8.s1
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Infrastructure FPGA Editor (XCV50E)
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Infrastructure FPGA Editor (XCV50E)
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PARBIT Tool - Example

• Utilization
• parbit option original partial target
• Example
• Visit http//www.arl.wustl.edu/arl/projects/
  fpx/parbit
• In the Download Section, right click on
  parbit-expl.tar

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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Demonstration
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PARBIT Tool - Demonstration

• Example (Cygwin Window)
• Run parbit
• parbit parbit-gask.opt gask_dhp.bit gask-part.bit
  gask_inf.bit
• Compare the sizes of gask_dhp.bit and
  gask-part.bit

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PARBIT Tool - Exercises

• Exercise 1
• Change the user parameters and generate a new
  partial configuration bitstream (gask-part2.bit)
  for one user module confined in a rectangular
  area with
• Start row 2
• Start col 5
• Height 3 rows
• Width 4 columns
• Target location Row 10, Col 15

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PARBIT Tool - Exercises

• Exercise 2
• Go to the PARBIT web page and get the project
  files for the gasket example (gask-design.tar)
• Modify the UCF files in order to change the
  location of the DHP user module two rows down
• Compile each project
• xflow p xcv50e-8-fg256 implement gask-i
  gask_dhp
• Open each project with the FPGA Editor
• fpga_editor gask_dhp.ncd
• Check the new logic locations
• Edit the file gask_dhp.ucf
• Add 2 to the row numbers (rX)

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Configuration Frames - Full Slice