Front End Electronics

1
Front End Electronics for the NOvA Neutrino
Detector John Oliver

• Long baseline neutrino experiment
• Fermilab (Chicago) to northern Minnesota (800
  km)
• 20-25 kTon Far and smaller Near detectors
  (Number given for 20 kTon in this document)

2
Electronics DAQ Organization

• L2 Manager L. Mualem / U. Minn
• Electronic Project Engineer J. Oliver /
  Harvard
• Front End Boards (FEBs)
• L3 Manager J.Oliver
• Elect Eng N. Felt
• Technician / designer S. Harder
• Test software J. Boehm
• DAQ FNAL
• Power Distribution Slow Controls U. Va

3
NOvA Far Detector

• 500,000 channels of liquid scintillator /
  wavelength shifting fiber cells
• Readout by 32 channel Avalanche Photo Diodes (10
  pf per pixel )
• Gain 100 _at_ -15C
• MIP 25 photoelectrons _at_ far end of cell
• ? 2,500 e / minimum ionizing signal
• Neutrino interactions in 10 ms spill every 2
  sec
• Signal dominated by cosmic rays 400 Hz/pixel

4
DAQ Heirarchy 64 FEBs to one Data Concentrator
FEBs
Beam
Beam
Beam
DAQ
5
DAQ Hierarchy

• 250 Data Concentrator Modules connected to CPU
  Farm via ethernet switches timing cables.
• All pixel hit data sent through Concentrators to
  CPU farm Timing signal take reverse path
• Each hit ? 32 bit timestamp (62.5 ns / bin,
  synched to Global timing system) pulseheight
• Global timing system with GPS receiver to
  correlate timing with NUMI beam spills
• All data are buffered for 10 seconds
• NUMI beamline spill is GPS timestamped
  transmitted to Far Detector via internet (as is
  now done in MINOS)
• In 10 sec buffer period, internet efficiency of
  spill signal is 100

6
Front End Board (FEB) Architecture
APD Module
DAQ
ADC
FPGA
ASIC
TE Cooler Control

• Thermoelectric cooler maintains 15C at APD
• ASIC integrates shapes 32 signal channels from
  APD
• Selectable risetime falltime constants
• ASICs 81 Multiplexers run _at_ 16 MHz to sample
  each channel at 500 ns/sample
• ASICs four outputs are continuously digitized
  by quad ADC _at_ 16 Msps and sent to FPGA
• 16,000 FEBs in NOvA Far Detector

7
Readout Electronics Noise

• APD noise
• Minimum noise dominated by APD leakage of 1
  2 nA _at_ -15C
• Dual Correlated Sampling would yield current
  (parallel) noise of 100 e rms _at_ DT 1 ms
• ? Keep APDs cold!
• Front end electronics noise
• Integrate signals in ASIC preamplifier with low
  noise
• Dual Correlated Sampling with controlled
  risetime constant of a few hundred ns would yield
  150 e rms ? Readout objective is to minimize
  both noise components
• Readout strategy
• Sample digitize each APD integrated signal
  continuously every 500 ns
• Digitize all samples off-chip (low cost external
  ADCs) send to FPGA
• Perform multiple correlated sampling filters in
  local FPGA
• Extract pulseheight timestamp locally for each
  hit
• Find in spill hits by timestamp in DAQ system
  (no trigger or spill signals on Front End Board)

8
32 ch ASIC (T. Zimmerman / FNAL)

• 16 MHz multiplexers
• 2 Msps per channel
• Adjustable risetime falltime
• Status
• Prototypes fabricated on TSMC 0.25u CMOS
• Tested work as per simulations

9
Signal Processing Pulseheight Timing

• Use multiple correlated pairs of samples
  centered on leading edge
• Weight the pairs by optimal coefficients
• Optimal coefficients depend on noise spectrum
• Parallel noise favors inner pair (small sampling
  time, small no of samples)
• Series noise favors multiples pairs (long
  risetime constant, large number of samples)
• Calibration
• Learn noise spectrum by sampling baseline (
  100us _at_ 2 - 16 Msps)
• Compute optimal digital filter parameters
  offline
• Download parameters back to FEBs

10
Filter simulation testing

• DSP filter tests
• Measurements from prototype electronics
• Simulated noise pulses
• Advantage ? Can easily vary noise sources
  (leakage current, thermal noise)

11
DSP example Timing extraction (N. Felt)

• Matched filter ? Convolute signal with stored
  ideal pulse shape
• Convolution yields sharply peaked function of
  time
• Apply interpolation filter

? 60ns timing resolution with 500ns sampled
signal (test data)
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Summary

• Flexible architecture Continuous digitization
  DSP
• 2 MSPS DSO on every channel Local analysis in
  FPGA
• Algorithms optimized off-line for pulseheight
  timing
• In-situ diagnostics Opens, shorts, APD high
  voltage, etc
• NUMI beam spill signal not required in-time at
  FEBs
• Spill signal sent to Far Detector via internet
  after spill
• All in-spill data sorted for time-stamp and saved
  to disc
• Low cost Front End Electronics
• Recent production electronics experience at
  Harvard
• ATLAS MDT Front End Electronics
• 75k chips produced tested
• 16k Mezzanine cards produced, tested, and
  delivered to ATLAS
• We gratefully acknowledge Weizmann Institute
  for Mezz Card production in Israel