DSP 'Swiss Army Knife'

1
DSP 'Swiss Army Knife'
Overall Project Objective General purpose
Digital Signal Processing chip

• Team M3
• Jacob Thomas
• Nick Marwaha
• Darren Shultz
• Craig T. LeVan
• Project Manager Zachary Menegakis

Stage 2 January 24, 2005
Architecture Proposal
2
Architecture Proposal

• General Purpose chip that performs a wide variety
  of functions
• Differencer
• Integrator
• Leaky Integrator
• First-Order Delay Network
• Audio Comb
• Etc
• Significance
• Applications in all fields of DSP (digital signal
  processing)
• Replaces commonly used algorithms based on the
  input coefficients
• Help increase efficiency of DSP circuit design
  via re-use

Stage 2 January 24, 2005
Architecture Proposal
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Final Algorithm1

• H(z ) (1 - c1z-N ) x

b0 b1z-1 b2z-2
1/a0 - a1z-1 - a2z-2
Stage 2 January 24, 2005
Architecture Proposal
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Initial Block Diagram
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Floating Point Modification
Stage 2 January 24, 2005
Architecture Proposal
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Floating Point Addition2
Stage 2 January 24, 2005
Architecture Proposal
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Refined Components
Floating Point Adder Detail
FP Multiplier
Stage 2 January 24, 2005
Architecture Proposal
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Benchmark Graphs
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Matlab Code

• function output swiss(z,a,b,c,N)a DSP "swiss
  army knife"
• n 0 1 zeros(1,98)
• max length(z)
• t -0.5 20.5/max 0.5-20.5/max
• Hz (1-cz.-N) . ((b(1)b(2)z.-1b(3)z.-2)
  ./ ...
• ( (1/a(1))-a(2)z.-1 - a(3)z.-2))
• plot(t,(abs(fftshift(Hz)).10)-12.5,'b')
• output real(fftshift(Hz).10)-12.5

Stage 2 January 24, 2005
Architecture Proposal
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Benchmark Graphs
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Matlab Results
a0 a1 1 a2 0 b0 1/N b1 b2 0 c1
1 N 8
Stage 2 January 24, 2005
Architecture Proposal
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Matlab Results
a0 1 a1 0 a2 0 b0 1 b1 -1 b2
0 c1 0
Stage 2 January 24, 2005
Architecture Proposal
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Matlab Results
a0 a1 1 a2 0 b0 1 b1 0 b2 0 c1
0
Stage 2 January 24, 2005
Architecture Proposal
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Matlab Results
a0 1 a1 1 - a a2 0 b0 a b1 0 b2
0 c1 0
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
module swiss (output reg 110 hz, input 110
z, // in floating point form i.e. SbE
11sign/106E/50S input 40 N, //
assumption that N is a positive integer input
10 c1, b0, b1, b2, a0, a1, a2) // bit1 for
sign, bit0 for value // assuming all inputs
except z are -1, 0, 1 // currently
non-renormalized floating point numbers
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
reg 110 zN // create an intermediate floating
point variable reg 110 one
12'b000000000001 reg 110 num
12'b000000000000 reg 110 numtemp
12'b000000000000 reg 110 den
12'b000000000000 reg 110 dentemp1
12'b000000000000 reg 110 dentemp2
12'b000000000000 reg 110 biquad
12'b000000000000 reg 40 diff reg 30
i always_at_(z, N, c1, b0, b1, b2, a0, a1,
a2) begin zN z// set intermediate variable zN
to value of input z
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
// performing operation zN if (N5'b00000) zN
12'b000000000001 else begin for(i4'b0001
iltN ii1) begin zN50 zN50
z50 zN106 zN106 z106 -
5'b01111 if(zN11 1 z11 0)
zN11 1 else if(zN11 0 z11
1) zN11 1 else zN11 0
end end // else !if(N5'b00000)
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
// performing operation c1/zN (or c1z-N) if
(c10 0) zN 12'b000000000000 else begin
zN50 6'b000001 / zN50 zN106
-zN106 5'b01111 if(c11 1 zN11
0) zN11 1 else if(c11 0
zN11 1) zN11 1 else zN11
0 end // else !if(c10 0)
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
// performing operation 1 - c1z-N // zN 1 -
c1z-N (comb filter) zN11zN11 if(one10
6gtzN106) begin diff40one106-zN106
zN50 zN50gtgtdiff end else
if(zN106gtone106) begin
diff40zN106-one106 one50
one50gtgtdiff end zN50zN50one50 one
110 12'b000000000001
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Code
// performing b1/z (or b1z-1) if (b10 0)
num110 12'b000000000000 else begin
num50 6'b000001 / z50 num106
-z106 5'b01111 if(b11 1 num11
0) num11 1 else if(b11 0
num11 1) num11 1 else
num11 0 end // else !if(b10
0) (...etc...)
Stage 2 January 24, 2005
Architecture Proposal
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Verilog Test Bench
module test_swiss (output n,z,b0,b1,b2,a0,a1,a2
input hz) initial begin
moniter(time,, "nb zb b0b b1b
b2b a0b a1b a2b hzb"
n,z,b0,b1,b2,a0,a1,a2,hz) 10/// (set input
values here) 10/// Inputs not well defined,
so no useful comparison to matlab results yet
10 10 end // initial
begin endmodule // test_swiss
Stage 2 January 24, 2005
Architecture Proposal
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Proposal Estimates
Waiting to re-calculate based on input
definitions and the bit-width of the floating
point numbers (12-point FP gives similar
estimates as above)
Stage 2 January 24, 2005
Architecture Proposal
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Marketing

• DSP
• Communications
• Wireless standard
• Video
• Noise reduction
• Audio
• Basic building block of acoustic audio effects
  such as acoustic echo simulation and plucked
  instrument synthesis
• May require floating point accuracy to be useful

Stage 2 January 24, 2005
Architecture Proposal
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Status

• Research (restarted)
• Transistor count (awaiting defined inputs)
• Block Diagram (altered for floating point)
• Verilog description (50)
• Layout (0)

• To Be Done
• Define inputs and FP bit-width
• Finalize Transistor count
• Refine block diagram
• Verilog / Layout / Verification

Stage 2 January 24, 2005
Architecture Proposal
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Design Decisions

• Move to floating point architecture
• Memory / Registers not included pending bit-width

Stage 2 January 24, 2005
Architecture Proposal
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Problems Questions

• Benchmark inputs not well defined
• Pushing the transistor count cap
• Hardware implementation of x-n and -1 not obvious
  (solved by floating point)
• Circuit may be a 'novelty' at only 8 bits(solved
  by floating point)

Stage 2 January 24, 2005
Architecture Proposal
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References

• 1 http//www.ecpe.vt.edu/fac_support/DSPCL/docs/
  SPMag04.pdf
• 2 http//www.cse.psu.edu/cg575/lectures/cse575-
  fpops.pdf