Project 2: Cadence Help

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Project 2 Cadence Help

• Fall 2005 EE 141
• Ke Lu

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Design Phase

• Estimate delay using stage effort. Example 8
  bit ripple adder driving a final load of 16.
• Rough estimate of Area. Sum over the size times
  LE of every gate.

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Schematics Using Hierarchy
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1. Transistor Level

• Remember to use nmos4 and pmos4.
• Make sure you have the right tech lib attached.
  0.24u process.
• Connect input and output pins accordingly.

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2. Creating Symbol from Schematic

• In Schematic view, click Design-gtCreate Cell
  View-gtFrom Cell View.
• Dont bother making the symbol shape pretty
  because Cadence will crash.

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3. Putting the Blocks Together

• Use i to instantiate symbols to build more
  complicated schematics.
• Use l hot key to label wire names to simplify
  connecting the blocks together. Example, VDD and
  GND.

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Extracting Netlist

• In Schematic view, open the analog environment
  window by clicking Tools-gt Analog Environment.
• Go to Setup-gt Environment and change the settings
  to hSpice and hierarchal.
• Next go to Setup-gt Simulator/Directory/Host and
  change the Project Directory.
• Finally, click Simulation-gt Netlist-gt Create
  Final
• Cadence will put the netlist in CELLNAME/
  hspiceS/extracted/netlist/hspiceFinal
• Fix the model file by adding .lib g25.mod TT,
  change TSMC25DN to NMOS, and edit the .OPTION
  statement.

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LAYOUT

• Pitfalls
• Doing LVS after laying out the entire adder.
• Not running DRC often.
• Not budgeting space for routing.
• Plan ahead to avoid these. Otherwise, Cadence
  will make life miserable.

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How to Pass LVS

• Plan ahead before laying out. Do stick diagrams
  first.
• Do LVS incrementally.
• Example, mirror adder.

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LVS, Extracting from Layout
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Summary

• START EARLY. Cadence will hang as more and more
  people use the machines.
• Check Design often, run DRC often. Catch bugs
  early.
• Worst case tpA 6 uS um2. You must do better.