Lecture 6 Circuit Level Power Estimation

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Lecture 6Circuit Level Power Estimation

• Domino CMOS Power Estimation
• Circuit-level methods
• ATPG methods
• Summary

• Michael L. Bushnell
• CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

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Domino CMOS Power Estimation

• Ignore direct-path short-circuit currents
• Average power over all circuit nodes
• Normalized power dissipation measure
• fanouti is fanouts of node i

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Domino Power Estimation

• F for n-type gate
• F for p-type gate

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Results for Method on NAND

• Z static CMOS, PZ Domino internal node,
  Z Domino output node

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Circuit Reliability

• Signal activity is a good measure of
  electro-migration and hot-electron degradation
  (happens only in saturation) in circuits
• Negative electro-migration leads to a hillock, or
  metal build-up, that can short adjacent metal
  lines
• Hot electron injection into gate oxide layer
  degrades gm and Vt, cumulative over time, limits
  useful life of transistor
• Mean time to failure (MTF) due to
  electro-migration
• Minimize electro-migration by minimizing

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Circuit Reliability (contd)

• J Average Current Density
• K has statistical distribution, independent of J
• Hgate Agate fgate hot electron degradation, W
  channel width, H and m
  independent of transistor currents
• T time that transistor has been operating
• Minimize reliability factor R to improve
  reliability
• R S Agate fgate activity x fanouts

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Circuit-Level Power EstimationNeed to consider
capacitance at internal gate nodes to obtain more
accurate power estimate
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Example CMOS Gate
X1
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Signal Connections to Minimize Power

• Gate presents variable capacitance to power
  ground, depending on logic inputs
• If signal A has high activity and signal B has
  low activity, then connect A to x2 and B to x1 to
  minimize power

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High-Level Power Estimation

• Method proposed by Landman and Rabaey for DSP
  circuits
• Stochastic modeling technique
• Uses relationship between bit-level probabilities
  and word-level statistics
• For speech, music, and images
• Least Significant Bits (LSBs) are uncorrelated in
  space/time with P 0.5 and a 0.25
• Independent of data distribution

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Word-Level Data Model
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Most Significant Bit Data Models

• F1 bivariate normal distribution function
• F01 univariate normal distribution function
• r1 lag 1 correlation coefficient
• Breakpoint equations (where MSB correlation
  starts)

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Information Theoretic Approaches

• Estimate power at Register Transfer Level
• Estimate entropy and use it to find signal
  activity
• Entropy H (x) defined in terms of signal
  probability p
• For discrete-valued signal x, with n values

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Activity Tracks Entropy

• Tracks entropy if temporal correlation can be
  ignored
• Theory not yet adequately developed

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Maximum Power Estimation

• Can be important for desktop applications
• Design of power and ground lines
• Determining line voltage drop
• Determining packaging requirements
• Estimating maximum current to determine inductive
  bounce in power supplies

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Automatic Test Pattern Generation (ATPG)-Based
Method

• Dynamic current due to 2 consecutive binary
  vectors
• T (g) is binary variable showing whether gate g
  switches
• Method
• Sort all gates by output C in non-increasing
  order
• Assign transitions to gates from list with
  largest output C or with the largest fanout
• Used 9-valued D algorithm to justify transitions
  with ATPG (automatic test-pattern generation)
  program
• Results more efficient and accurate than
  simulation-based techniques for maximum power
  estimation

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Steepest Descent Method

• Approximate power as
• F (g) gate fanouts
• T (g) transition count at gate g output
• Method
• Use static timing analyzer to create time
  sequences for given circuit
• Propagate input time sequence in level order from
  inputs through gates to circuit outputs

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Problem Formulation

• Transform to continuous variable domain by
  transforming Boolean operators into arithmetic
  operators and by adding an unbiasing term to the
  objective function

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Steepest Descent Search Strategy

• Calculate gradient of objective (cost) function
  at a starting point
• Move along direction of gradient until objective
  function starts to decrease, at which point we go
  back to Step 1
• Stopping criterion
• Search reaches relative maximum point with 0
  gradient
• Search is stuck on hypercube boundary, with
  gradient normal to the boundary
• Avoid local maxima
• Choose different starting point
• Increase w (weight of non-biasing term in
  objective function) to change shape of objective
  function

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ATPG vs. Gradient vs. Simulation Methods Unit
Delay Model
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ATPG vs. Gradient vs. Simulation Methods Fanout
Delay Model
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CPU Time Comparisons for Unit Delay Model Circuits
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CPU Time Comparisons for Fanout Delay Model
Circuits
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Comparison of Estimators

• Gradient optimization approach advantages
• Tighter lower bound for maximum power
• Much faster than simulation
• Can use complex gate delay models that ATPG
  methods cannot use
• Gets better max. power estimate than ATPG for 24
  out of 40 circuits
• Disadvantages
• Slower than ATPG approach

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Genetic Algorithm Method

• Work of Hsiao, Rudnick, and Patel
• Genetic algorithm computes good local solutions
  to power estimation, and then evolves and mutates
  solutions to find even better solutions
• Estimates good lower bounds of
• Maximum power per cycle
• Maximum sustained power under different delay
  models
• May be slow, so it may need parallel computers

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Summary of Power Estimation

• Circuit-level and High-level power estimators
  exist
• Maximum power estimated with ATPG tools, using
  steepest-descent gradient descent, or genetic
  algorithms